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1. 发明申请

WO2008036810A3 BI-LAYER CAPPING OF LOW-K DIELECTRIC FILMS 审中-公开
标题翻译：低K电介质薄膜的双层封装
公开(公告)号：WO2008036810A3
公开(公告)日：2008-06-12
申请号：PCT/US2007079020
申请日：2007-09-20
申请人： APPLIED MATERIALS INC , XU PING , BENCHER CHRISTOPHER DENNIS
发明人： XU PING , BENCHER CHRISTOPHER DENNIS
IPC分类号： H01L21/02 , H01L21/56 , H01L23/28
CPC分类号： H01L21/76829 , C23C16/30 , C23C16/45523 , H01L21/02126 , H01L21/022 , H01L21/02216 , H01L21/02274 , H01L21/0234 , H01L21/02348 , H01L21/02351 , H01L21/02362 , H01L21/3122 , H01L21/31633 , H01L21/76835
摘要： A method is provided for processing a substrate surface by delivering a first gas mixture comprising a first organosilicon compound, a first oxidizing gas, and one or more hydrocarbon compounds into a chamber at deposition conditions sufficient to deposit a first low dielectric constant film on the substrate surface. A second gas mixture having a second organosilicon compound and a second oxidizing gas is delivered into the chamber at deposition conditions sufficient to deposit a second low dielectric constant film on the first low dielectric constant film. The flow rate of the second oxidizing gas into the chamber is increased, and the flow rate of the second organosilicon compound into the chamber is decreased to deposit an oxide rich cap on the second low dielectric constant film.
摘要翻译：提供了一种通过将包含第一有机硅化合物，第一氧化气体和一种或多种烃化合物的第一气体混合物输送到室中的方法来处理衬底表面，该沉积条件足以在衬底上沉积第一低介电常数膜表面。具有第二有机硅化合物和第二氧化气体的第二气体混合物在足以在第一低介电常数膜上沉积第二低介电常数膜的沉积条件下被输送到室中。进入室内的第二氧化气体的流量增加，第二有机硅化合物进入室的流量减少，从而在第二低介电常数膜上沉积氧化物富集盖。

2. 发明申请

WO2005076081A2 RETICLE FABRICATION USING A REMOVABLE HARD MASK 审中-公开
标题翻译：使用可移除的硬掩模进行制造
公开(公告)号：WO2005076081A2
公开(公告)日：2005-08-18
申请号：PCT/US2005002563
申请日：2005-01-27
申请人： APPLIED MATERIALS INC , BENCHER CHRISTOPHER DENNIS , MONTGOMERY MELVIN WARREN , BUXBAUM ALEXANDER , LEE YUNG-HEE YVETTE , DING JIAN , ALMOGY GILAD , YEH WENDY H
发明人： BENCHER CHRISTOPHER DENNIS , MONTGOMERY MELVIN WARREN , BUXBAUM ALEXANDER , LEE YUNG-HEE YVETTE , DING JIAN , ALMOGY GILAD , YEH WENDY H
IPC分类号： G03F1/08 , G03F7/09
CPC分类号： G03F1/68 , G03F1/46 , G03F1/80
摘要： We have reduced the critical dimension bias for reticle fabrication. Pattern transfer to the radiation-blocking layer of the reticle substrate essentially depends upon use of a hard mask to which the pattern is transferred from a photoresist. The photoresist pull back which occurs during pattern transfer to the hard mask is minimalized. In addition, a hard mask material having anti-reflective properties which are matched to the reflective characteristics of the radiation-blocking layer enables a reduction in critical dimension size and an improvement in the pattern feature integrity in the hard mask itself. An anti-reflective hard mask layer left on the radiation-blocking layer provides functionality when the reticle is used in a semiconductor device manufacturing process.
摘要翻译：我们已经降低了光罩制造的临界尺寸偏差。图案转移到掩模版衬底的辐射阻挡层基本上取决于使用图案从光致抗蚀剂转移到的硬掩模。在图案转移到硬掩模期间发生的光致抗蚀剂拉回被最小化。另外，具有与辐射阻挡层的反射特性相匹配的抗反射特性的硬掩模材料使得能够减小临界尺寸尺寸并且改善硬掩模本身中的图案特征完整性。当掩模版用于半导体器件制造工艺时，留在辐射阻挡层上的抗反射硬掩模层提供了功能。

3. 发明申请

WO2009137199A2 BORON NITRIDE AND BORON-NITRIDE DERIVED MATERIALS DEPOSITION METHOD 审中-公开
标题翻译：硼氮化物和硼 - 氮化物衍生材料沉积方法
公开(公告)号：WO2009137199A2
公开(公告)日：2009-11-12
申请号：PCT/US2009039356
申请日：2009-04-02
申请人： APPLIED MATERIALS INC , BALSEANU MIHAELA , BENCHER CHRISTOPHER DENNIS , CHEN YONGMEI , ROFLOX ISABELITA , XIA LI-QUN , WITTY DEREK R , MIAO LI YAN , NGUYEN VICTOR
发明人： BALSEANU MIHAELA , BENCHER CHRISTOPHER DENNIS , CHEN YONGMEI , ROFLOX ISABELITA , XIA LI-QUN , WITTY DEREK R , MIAO LI YAN , NGUYEN VICTOR
IPC分类号： H01L21/205 , H01L21/3065 , H01L21/336
CPC分类号： H01L21/31144 , H01L21/3086 , H01L21/3105 , H01L21/31111 , H01L21/31122 , H01L21/318 , H01L21/76832 , H01L29/4966
摘要： A method and apparatus are provided to form spacer materials adjacent substrate structures. In one embodiment, a method is provided for processing a substrate including placing a substrate having a substrate structure adjacent a substrate surface in a deposition chamber, depositing a spacer layer on the substrate structure and substrate surface, and etching the spacer layer to expose the substrate structure and a portion of the substrate surface, wherein the spacer layer is disposed adjacent the substrate structure. The spacer layer may comprise a boron nitride material. The spacer layer may comprise a base spacer layer and a liner layer, and the spacer layer may be etched in a two-step etching process.
摘要翻译：提供了一种方法和设备以形成与衬底结构相邻的间隔物材料。在一个实施例中，提供了一种用于处理衬底的方法，该方法包括：将具有与衬底表面相邻的衬底结构的衬底放置在沉积室中;在衬底结构和衬底表面上沉积间隔层;以及刻蚀间隔层以暴露衬底结构和衬底表面的一部分，其中间隔层设置在衬底结构附近。间隔层可以包含氮化硼材料。间隔层可以包括基础间隔层和衬垫层，并且间隔层可以在两步刻蚀工艺中刻蚀。

4. 发明申请

WO2008027845A3 DOPANT ACTIVATION IN DOPED SEMICONDUCTOR SUBSTRATES 审中-公开
标题翻译：掺杂半导体衬底中的掺杂剂活化
公开(公告)号：WO2008027845A3
公开(公告)日：2008-06-19
申请号：PCT/US2007076910
申请日：2007-08-27
申请人： APPLIED MATERIALS INC , MUNRO JEFFREY C , NEMANI SRINIVAS D , LEE YOUNG S , MENEZES MARLON , BENCHER CHRISTOPHER DENNIS , PARIHAR VIJAY
发明人： MUNRO JEFFREY C , NEMANI SRINIVAS D , LEE YOUNG S , MENEZES MARLON , BENCHER CHRISTOPHER DENNIS , PARIHAR VIJAY
IPC分类号： C23C16/00 , H05H1/24
CPC分类号： H01L21/268 , C23C16/26 , C23C16/505 , C23C16/56 , H01L21/26513
摘要： Methods are disclosed for activating dopants in a doped semiconductor substrate. A carbon precursor is flowed into a substrate processing chamber within which the doped semiconductor substrate is disposed. A plasma is formed from the carbon precursor in the substrate processing chamber. A carbon film is deposited over the substrate with the plasma. A temperature of the substrate is maintained while depositing the carbon film less than 500°c. The deposited carbon film is exposed to electromagnetic radiation for a period less than 10 ms, and has an extinction coefficient greater than 0.3 at a wavelength comprised by the electromagnetic radiation.
摘要翻译：公开了用于激活掺杂半导体衬底中的掺杂剂的方法。碳前体流入设置有掺杂半导体衬底的衬底处理室中。在衬底处理室中由碳前体形成等离子体。用等离子体在衬底上沉积碳膜。在沉积小于500℃的碳膜时保持衬底的温度。沉积的碳膜暴露于电磁辐射下的时间小于10ms，并且在电磁辐射所包含的波长处具有大于0.3的消光系数。

5. 发明公开

KR20180039180A 스텝 크기 변경을 통한 라인 에지 거칠기 감소 审中-公开
公开(公告)号：KR20180039180A
公开(公告)日：2018-04-17
申请号：KR20187009552
申请日：2016-08-08
申请人： APPLIED MATERIALS INC
发明人： LAIDIG THOMAS L , JOHNSON JOSEPH , BENCHER CHRISTOPHER DENNIS
IPC分类号： G03F7/20
CPC分类号： G03F7/2051
摘要： 제조프로세스에서기판에마스크리스리소그래피패턴들을적용하는능력에관한이미지정정애플리케이션이개시된다. 본명세서에설명된실시예들은기판상의불균일한이미지패턴들을정정하는소프트웨어애플리케이션플랫폼에관한것이다. 이애플리케이션플랫폼방법은 DMD 내의거울들의적어도하나의전체컬럼을디스에이블하는단계 - 상기 DMD는복수의컬럼을갖고각 컬럼은복수의거울을가짐 -, 상기기판의제1 부분을전자기복사의제1 숏에노출시키는단계, 상기기판의제2 부분을전자기복사의제2 숏에노출시키는단계, 및상기기판이완전히처리될때까지상기기판의제2 부분을제2 숏에노출시키는것을반복하는단계를포함한다.

6. 发明公开

KR20200136046A 기판 처리 동안의 선량 맵들 및 피쳐 크기 맵들의 제조 및 사용 审中-公开
公开(公告)号：KR20200136046A
公开(公告)日：2020-12-04
申请号：KR20207033802
申请日：2019-03-27
申请人： APPLIED MATERIALS INC
发明人： BENCHER CHRISTOPHER DENNIS , JOHNSON JOSEPH R
IPC分类号： G03F7/20 , G03F1/76
摘要： 본원에논의되는시스템들및 방법들은, 선량을사용하여피쳐들을임계치수들의세트또는세트들로형성하도록리소그래피및 마이크로리소그래피동안기판들을패터닝하는것에관한것이다. 선량맵들은, 기판들을패터닝하는데 이용되는복수의동작들에서의프로세스변동을처리하기위해제조동안포착된이미지들에기반하여생성된다. 선량맵들은, 이미징프로그램들과함께사용되어, 피쳐들을임계치수들의세트또는세트들로생성하고보상하지않으면올바르지않은임계치수형성을초래할수 있는업스트림또는다운스트림동작들을보상하기위해, 기판의다양한구역들에인가되는전압들을조율한다.

7. 发明公开

KR20200137031A 고체 상태 방출기 어레이들을 사용하는 시스템들 및 방법들 审中-公开
公开(公告)号：KR20200137031A
公开(公告)日：2020-12-08
申请号：KR20207034120
申请日：2019-02-05
申请人： APPLIED MATERIALS INC
发明人： BENCHER CHRISTOPHER DENNIS , JOHNSON JOSEPH R
IPC分类号： G03F7/20 , G03F1/76
摘要： 본개시내용의실시예들은고체상태방출기디바이스를사용하는개선된포토리소그래피시스템들및 방법들을제공한다. 고체상태방출기디바이스는, 복수의수평행들및 수직열들로배열된고체상태방출기들의어레이를포함한다. 개선된필드밝기균일성및 스티칭을위해, 고체상태방출기들의각각의군, 예를들어, 고체상태방출기들의전체행 또는열의가변강도가제어가능하다. 가변강도를제어하는것은, 예를들어, 포토리소그래피처리동안중첩노출들을수용하기위해어레이의중간으로부터어레이의에지들까지밝기를감쇠시키기위해서, 고체상태방출기들의각각의행들에인가되는신호, 예컨대, 전압을변화시키는것을포함한다.

8. 发明专利

JP2001257206A METHOD AND APPARATUS FOR REDUCING FIXED CHARGE IN A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2001257206A
公开(公告)日：2001-09-21
申请号：JP2000372952
申请日：2000-12-07
申请人： APPLIED MATERIALS INC
发明人： HUANG JUDY H , BENCHER CHRISTOPHER DENNIS , RATHI SUDHA
IPC分类号： C23C16/42 , C23C16/02 , C23C16/44 , C23C16/455 , H01L21/20 , H01L21/314 , H01L21/316 , H01L21/768 , H01L23/522
摘要： PROBLEM TO BE SOLVED: To provide a method and an apparatus for manufacturing an IC which is improved in insulation characteristic in such a way that no charge trapping phenomenon occurs on the interface between a dielectric material having a low (k) and another insulating material. SOLUTION: The method for manufacturing the IC includes a step 704 of forming a first layer; a step 706 of forming a transition layer on the first layer by making a deposition gas, a dilution gas, and a conversion gas to flow on the surface of the first layer; and a step 708 of stopping the flowing of the conversion gas in steps. The method also includes a step 710 of forming a second layer on the transition layer. The deposition, dilution, and conversion gases are preferably trimethylsilane, helium, and N2O, respectively, and the method is performed via chemical vapor deposition or plasma enhanced chemical vapor deposition. The device for manufacturing the IC is provided with a first insulating layer, a transition layer deposited upon the insulating layer, and a second insulating layer. The transition layer improves the adhesion between the insulating layers and reduces the amount of electrical charges trapped between the insulating layers.

9. 发明专利

JP2010103539A Self alignment multiple pattern formation for advanced microscopic size contact 审中-公开
标题翻译：自动对准多个高级显微镜尺寸联系的多模式
公开(公告)号：JP2010103539A
公开(公告)日：2010-05-06
申请号：JP2009243617
申请日：2009-10-22
申请人： Applied Materials Inc , アプライドマテリアルズインコーポレイテッドApplied Materials,Incorporated
发明人： MEBARKI BENCHERKI , LI YAN MIAO , BENCHER CHRISTOPHER DENNIS , SHU JEN
IPC分类号： H01L21/768 , H01L21/28 , H01L21/3065
CPC分类号： H01L21/0337
摘要： PROBLEM TO BE SOLVED: To provide a processing sequence which increases the density of a featured section on a substrate. SOLUTION: One embodiment is related to a method of forming a pattern formation feature section which has more reduced pitches in two dimensions on the substrate, as compared with pitches realized using a standard photolithography processing technique which uses a single high resolution photomask. A spacer layer is formed on a two dimensional square grid of a core, and the layer has a thickness chosen so that a dimple is left at the center of four cores in the corner parts of a square. The spacer layer is etched back so as to expose the substrate at the center of the square. Removing the core material doubles the pattern density of a photolithography defining grid of the core. The region of the exposed substrate is filled up again with the core material, and the above processing is repeated so that the pattern density becomes fourfold. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供增加基板上的特征部分的密度的处理顺序。解决方案：与使用使用单个高分辨率光掩模的标准光刻处理技术实现的间距相比，一种实施方式涉及形成图案形成特征部分的方法，该图案形成特征部分在基板上具有更小的二维间距。在芯的二维正方形网格上形成间隔层，并且该层具有选择的厚度，使得在正方形的角部中的四个芯的中心处留有凹坑。将间隔层回蚀刻，以便在正方形的中心露出衬底。去除芯材料使芯片的光刻图案的图案密度加倍。暴露的基板的区域再次用芯材料填充，并且重复上述处理，使得图案密度变为四倍。版权所有（C）2010，JPO＆INPIT

10. 发明专利

JP2010114424A Integral patterning of large feature portion and array using spacer mask patterning process flow 有权
标题翻译：大型特征部分的集成方案和使用间隔板掩模过程流程的阵列
公开(公告)号：JP2010114424A
公开(公告)日：2010-05-20
申请号：JP2009217751
申请日：2009-09-18
申请人： Applied Materials Inc , アプライドマテリアルズインコーポレイテッドApplied Materials,Incorporated
发明人： BENCHER CHRISTOPHER DENNIS , TANG JING
IPC分类号： H01L21/3065 , G03F1/08 , H01L21/027
CPC分类号： H01L21/3086 , H01L21/3088 , Y10S438/95
摘要： PROBLEM TO BE SOLVED: To provide a method of forming a patterned feature portion on a substrate having a higher density (that is, a low pitch) as compared to what is possible using a standard photolithography processing technique using a single high-resolution photomask, while changing both the width of the patterned feature portion and a spacing (trench width) between the patterned features portions are in an integrated circuit.
SOLUTION: The method of forming the patterned feature portion includes the steps of: forming a core layer and a protective layer on the substrate (S252); transferring a resist pattern to the core layer (S256); removing the overall protective layer on a narrow pattern and a part of the protective layer on a wide pattern by resist removing self-limiting etching (S260); forming a conformal dielectric layer and performing directional etching (S264); and then removing the core layer from a narrow pattern structure (S268).
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种在具有较高密度（即，低间距）的基底上形成图案化特征部分的方法，与使用单个高分辨率的标准光刻处理技术相比，同时改变图案化特征部分的宽度和图案化特征部分之间的间隔（沟槽宽度）在集成电路中。解决方案：形成图案特征部分的方法包括以下步骤：在衬底上形成芯层和保护层（S252）; 将抗蚀剂图案转印到芯层（S256）上; 通过抗蚀剂去除自限蚀刻去除在宽图案上的窄图案和保护层的一部分上的整体保护层（S260）; 形成保形介电层并执行定向蚀刻（S264）; 然后从窄图案结构去除芯层（S268）。版权所有（C）2010，JPO＆INPIT

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