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1. 发明申请

WO2002091583A1 MODIFIED REPETITIVE CELL MATCHING TECHNIQUE FOR INTEGRATED CIRCUITS 审中-公开
标题翻译：用于集成电路的改进的重复细胞匹配技术
公开(公告)号：WO2002091583A1
公开(公告)日：2002-11-14
申请号：PCT/US2002/011772
申请日：2002-04-12
申请人： ANALOG Devices, INC
发明人： KRANZ, Rodney, Louis , LANE, Charles, D. , JARMAN, David
IPC分类号： H03M1/36
CPC分类号： H03M1/0678 , H03M1/36
摘要： An integrated circuit including a number of repetitive cells for producing output signals in response to respective inputs, each cell(14,16,18) having associated with it an output circuit responsive to the cell output signal to produce an output circuit output signal, each of the output circuits including a circuit device having two terminals to provide for the flow therethrough of a current from an associated current supply(137) and producing a corresponding output signal; the improvement for producing the effectsof cell mismatch and output circuit mismatch including an impedance network(150), having a set of impedance elements each connected between corresponding terminals or respective pairs of the circuits with each circuit device forming a part of a respective output circuit(110,112), the impedance elements reducing the efforts of cell mismatch and output circuit mismatch on the output signals; there maybe one impedance network which accommodates mismatch es in both the cell and output circuits or there may be one impedance network to accommodate cell mismatch and another to accommodate output circuit mismatch.
摘要翻译：一种集成电路，包括响应于相应输入产生输出信号的多个重复单元，每个单元（14,16,18）具有与其相关联的输出电路，响应于单元输出信号以产生输出电路输出信号，每个输出电路包括具有两个端子的电路装置，用于提供来自相关电流源（137）的电流流过并产生相应的输出信号; 用于产生电池失配和输出电路失配的影响的改进，包括阻抗网络（150），其具有各自连接在相应端子或相应电路对之间的一组阻抗元件，每个电路装置形成相应输出电路的一部分（ 110,112），阻抗元件减少了输出信号的电池失配和输出电路失配的努力; 可能存在一个阻抗网络，其适应电池和输出电路中的不匹配，或者可以存在一个阻抗网络以适应电池失配，另一个阻抗网络适应输出电路不匹配。

2. 发明申请

WO1991004609A1 PARALLEL ANALOG-TO-DIGITAL CONVERTER USING 2(n-1) COMPARATORS 审中-公开
标题翻译：使用2（N-1）比较器的并行模拟到数字转换器
公开(公告)号：WO1991004609A1
公开(公告)日：1991-04-04
申请号：PCT/US1990005295
申请日：1990-09-18
申请人： ANALOG DEVICES, INC.
发明人： ANALOG DEVICES, INC. , LANE, Charles, D.
IPC分类号： H03M01/36
CPC分类号： H03M1/206 , H03M1/361
摘要： The invention comprises an n-bit analog-to-digital flash converter comprising 2n/2 input comparators, each having a first input coupled to receive the analog voltage to be converted and a second input coupled to a different reference voltage. The reference voltages of each consecutive input comparator are spaced apart two LSBs of the converter. Each input comparator has two outputs, OUT and an inverted version thereof, O^¨B7U^¨B7T^¨B7. 2n-1 consecutive latches are provided. Every other latch receives at its inputs the OUT and O^¨B7U^¨B7T^¨B7 signals from a single associated input comparator. All other latches receive the OUT signal of one of the input comparators and the O^¨B7U^¨B7T^¨B7 signal of an adjacent input comparator. The latches having inputs coupled to the OUT and O^¨B7U^¨B7T^¨B7 signals of a single input comparator produce a comparison output which change state every two LSBs of the converter and the latches having one input coupled to the OUT signal of one input comparator and the O^¨B7U^¨B7T^¨B7 signal of an adjacent input comparator produce comparison signals which change state halfway between the output signals of the adjacent latches. Thus, a comparison output is provided for every LSB of the full scale range of the converter using only 2n/2 input comparators.

3. 发明申请

WO1997022180A1 HIGH SPEED SATURATION PREVENTION FOR SATURABLE CIRCUIT ELEMENTS 审中-公开
标题翻译：可耐受电路元件的高速饱和度预防
公开(公告)号：WO1997022180A1
公开(公告)日：1997-06-19
申请号：PCT/US1996019533
申请日：1996-12-09
申请人： ANALOG DEVICES, INC.
发明人： ANALOG DEVICES, INC. , TICE, Thomas, E. , CROOK, David, T. , KATTMANN, Kevin, M. , LANE, Charles, D.
IPC分类号： H03K05/153
CPC分类号： H03M1/129 , H03M1/145
摘要： A protection circuit inhibits saturation and damage of sensitive circuit elements (54) when an input signal goes out of a nominal input range. The protection circuit includes an out-of-range detector (52) which compares the input signal to reference levels to determine if it is within the range. If it is not, a control circuit (62, 64) substitutes a supplemental signal that is slightly out of range, but not so far out of range as to cause any substantial saturation. Supplemental signal sources that produce supplemental signals slightly outside the high and low ends of the range with error margins, not more than about 750 mV, that lie just outside the range; an out-of-range input is replaced by the supplemental signal with the closest value. The invention is particularly applicable to multi-step/subranging analog-to-digital/converters.
摘要翻译：当输入信号超出额定输入范围时，保护电路抑制敏感电路元件（54）的饱和和损坏。保护电路包括超出范围检测器（52），其将输入信号与参考电平进行比较以确定其是否在该范围内。如果不是，则控制电路（62,64）代替略微超出范围但不超出范围的补充信号，以引起任何实质的饱和。补充信号源产生稍微超出范围的高端和低端的补充信号，误差范围不大于约750mV，处于范围之外; 超范围输入由具有最接近的值的补充信号代替。本发明特别适用于模数/转换器的多级/次级。

4. 发明申请

WO1996021271A1 OPEN-LOOP, DIFFERENTIAL AMPLIFIER WITH ACCURATE AND STABLE GAIN 审中-公开
标题翻译： OPEN-LOOP，具有精确和稳定增益的差分放大器
公开(公告)号：WO1996021271A1
公开(公告)日：1996-07-11
申请号：PCT/US1995014088
申请日：1995-11-01
申请人： ANALOG DEVICES, INC.
发明人： ANALOG DEVICES, INC. , TICE, Thomas, E. , CROOK, David, T. , KATTMAN, Kevin, M. , LANE, Charles, D.
IPC分类号： H03F03/45
CPC分类号： H03F3/45098 , H03F1/083 , H03F3/45085 , H03F2203/45392 , H03F2203/45702 , H03F2203/45722 , H03F2203/5003 , H03M1/16
摘要： Open-loop differential amplifiers (120, 140) are disclosed which have accurate and stable gain. The gain of these amplifiers is substantially insensitive to the effects of small-signal emitter resistance re, current gain beta and Early voltage VA. Thus, their gain can be accurately set by resistance ratios which makes them particularly useful in integrated circuits. These advantages are obtained with an output differential pair (67) that has cross-coupled base and collector terminals. In addition, resistors (141, 143, 148, 150) and a current source (146) associated with this differential pair are related to like elements (27, 28, 24, 25 and 26) that are associated with an input differential pair (21) by disclosed numerical ratios, e.g., the nominal gain G of the amplifier. Versions of the amplifiers can be adapted for use as a residue amplifier (162) in a subranging A/D converter (160).
摘要翻译：公开了具有准确和稳定增益的开环差分放大器（120,140）。这些放大器的增益对小信号发射极电阻re，电流增益β和早期电压VA的影响基本不敏感。因此，它们的增益可以通过电阻比来精确地设定，这使得它们在集成电路中特别有用。这些优点通过具有交叉耦合的基极和集电极端子的输出差分对（67）获得。另外，与该差分对相关联的电阻（141,143,148,150）和电流源（146）与与输入差分对相关联的相似元件（27,28,24,25和26）有关， 21）通过公开的数值比例，例如放大器的标称增益G。放大器的版本可以适用于亚排A / D转换器（160）中的残留放大器（162）。

5. 发明申请

WO1997032400A1 HIGH BANDWIDTH PARALLEL ANALOG-TO-DIGITAL CONVERTER 审中-公开
标题翻译：高带宽并行模拟数字转换器
公开(公告)号：WO1997032400A1
公开(公告)日：1997-09-04
申请号：PCT/US1997003043
申请日：1997-02-26
申请人： ANALOG DEVICES, INC. (ADI)
发明人： ANALOG DEVICES, INC. (ADI) , HUNTLEY, Roger, B., Jr. , TICE, Thomas, E. , LANE, Charles, D.
IPC分类号： H03M01/36
CPC分类号： H03M1/0682 , H03M1/363
摘要： A new differential ladder/comparator circuit reduces settling time delays in parallel analog-to-digital converters. A parallel analog-to-digital converter includes a pair of differential resistor ladders (L3, L4) having their taps connected to a group of comparators. The comparators produce digital "thermometer" scale outputs corresponding to analog signals impressed upon the differential ladders. By employing double-value resistors to form the "rungs" of the ladders and by connecting the comparators to the ladders taps in a way that increases the number of comparator inputs connected to the ladders' lower-order taps and decreases the number of comparator inputs connected to the ladders' higher order taps, the input impedance presented by the ladder/comparator combination is reduced in comparison with conventional differential ladder parallel ADCs. Additionally, input signal are superimposed on the ladders by drivers (Q1, Q2) which, in a preferred embodiment, present lower output impedances to the ladders than prior art drivers, further improving the bandwidth of the ADC.
摘要翻译：新的差分梯形图/比较器电路减少了并行模数转换器的稳定时间延迟。并行模数转换器包括一对具有连接到一组比较器的抽头的差分电阻梯（L3，L4）。比较器产生对应于印在差分梯子上的模拟信号的数字“温度计”量程输出。通过采用双值电阻器来形成梯子的“梯级”，并通过将比较器连接到梯形抽头，以增加连接到梯级低阶抽头的比较器输入的数量并减少比较器输入的数量连接到梯子的高阶抽头，与传统的差分梯形并行ADC相比，梯形图/比较器组合所呈现的输入阻抗减小。另外，在优选实施例中，驱动器（Q1，Q2）将输入信号叠加在梯子上，驱动器（Q1，Q2）比现有技术的驱动器向梯子呈现较低的输出阻抗，进一步提高了ADC的带宽。

6. 发明申请

WO1996016476A1 HIGH SPEED OVERVOLTAGE DETECTION AND PROTECTION CIRCUIT 审中-公开
标题翻译：高速过压检测和保护电路
公开(公告)号：WO1996016476A1
公开(公告)日：1996-05-30
申请号：PCT/US1995014158
申请日：1995-11-01
申请人： ANALOG DEVICES, INC. (ADI)
发明人： ANALOG DEVICES, INC. (ADI) , TICE, Thomas, E. , CROOK, David, T. , KATTMAN, Kevin, M. , LANE, Charles, D.
IPC分类号： H03K05/153
CPC分类号： H03G11/00 , H03F1/52
摘要： An overvoltage protection circuit protects against saturation and damage of sensitive circuitry elements. The protection circuit includes an out-of-range detector (52) which compares an input signal to reference levels to determine if it is within a predetermined range of acceptable inputs. If the input is determined not to be within this range, a control circuit (62, 64) substitutes a supplemental signal within the range for the input signal. Digital correction can be provided to correct the output of the sensitive circuit element while the supplemental signal is being substituted. Numerous circuit designs may be used to implement the protection scheme.
摘要翻译：过压保护电路可以防止敏感电路元件的饱和和损坏。保护电路包括超出范围检测器（52），其将输入信号与参考电平进行比较，以确定其是否在可接受的输入的预定范围内。如果确定输入不在该范围内，则控制电路（62,64）将输入信号范围内的补充信号代入。可以提供数字校正以在补充信号被替代时校正敏感电路元件的输出。可以使用许多电路设计来实现保护方案。

7. 发明授权

EP1386402B1 MODIFIED REPETITIVE CELL MATCHING TECHNIQUE FOR INTEGRATED CIRCUITS 有权
标题翻译：改进的，重复的细胞比较时技术集成电路
公开(公告)号：EP1386402B1
公开(公告)日：2008-11-05
申请号：EP02769266.4
申请日：2002-04-12
申请人： Analog Devices, Inc.
发明人： KRANZ, Rodney, Louis , LANE, Charles, D. , JARMAN, David
IPC分类号： H03M1/36 , H03M1/06
CPC分类号： H03M1/0678 , H03M1/36
摘要： An integrated circuit including a number of repetitive cells for producing output signals in response to respective inputs, each cell(14,16,18) having associated with it an output circuit responsive to the cell output signal to produce an output circuit output signal, each of the output circuits including a circuit device having two terminals to provide for the flow therethrough of a current from an associated current supply(137) and producing a corresponding output signal; the improvement for producing the effectsof cell mismatch and output circuit mismatch including an impedance network(150), having a set of impedance elements each connected between corresponding terminals or respective pairs of the circuits with each circuit device forming a part of a respective output circuit(110,112), the impedance elements reducing the efforts of cell mismatch and output circuit mismatch on the output signals; there maybe one impedance network which accommodates mismatch es in both the cell and output circuits or there may be one impedance network to accommodate cell mismatch and another to accommodate output circuit mismatch.

8. 发明公开

EP1386402A1 MODIFIED REPETITIVE CELL MATCHING TECHNIQUE FOR INTEGRATED CIRCUITS 有权
标题翻译：改进的，重复的细胞比较时技术集成电路
公开(公告)号：EP1386402A1
公开(公告)日：2004-02-04
申请号：EP02769266.4
申请日：2002-04-12
申请人： Analog Devices, Inc.
发明人： KRANZ, Rodney, Louis , LANE, Charles, D. , JARMAN, David
IPC分类号： H03M1/36
CPC分类号： H03M1/0678 , H03M1/36
摘要： An integrated circuit including a number of repetitive cells for producing output signals in response to respective inputs, each cell(14,16,18) having associated with it an output circuit responsive to the cell output signal to produce an output circuit output signal, each of the output circuits including a circuit device having two terminals to provide for the flow therethrough of a current from an associated current supply(137) and producing a corresponding output signal; the improvement for producing the effectsof cell mismatch and output circuit mismatch including an impedance network(150), having a set of impedance elements each connected between corresponding terminals or respective pairs of the circuits with each circuit device forming a part of a respective output circuit(110,112), the impedance elements reducing the efforts of cell mismatch and output circuit mismatch on the output signals; there maybe one impedance network which accommodates mismatch es in both the cell and output circuits or there may be one impedance network to accommodate cell mismatch and another to accommodate output circuit mismatch.

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