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1. 发明申请

WO2007033243A2 SEMICONDUCTOR PACKAGE HAVING PLATE INTERCONNECTIONS 审中-公开
标题翻译：半导体封装具有板互连
公开(公告)号：WO2007033243A2
公开(公告)日：2007-03-22
申请号：PCT/US2006/035641
申请日：2006-09-12
申请人： ALPHA & OMEGA SEMICONDUCTOR LTD. , SUN, Ming , SHI, Lei , HO, Yueh-Se , LIU, Kai , ZHANG, Xiaotian
发明人： SUN, Ming , SHI, Lei , HO, Yueh-Se , LIU, Kai , ZHANG, Xiaotian
IPC分类号： H01L23/48 , H01L23/28
CPC分类号： H01L23/49524 , H01L23/49562 , H01L24/37 , H01L24/40 , H01L24/41 , H01L2224/32245 , H01L2224/37011 , H01L2224/40095 , H01L2224/40245 , H01L2224/40249 , H01L2224/4103 , H01L2224/84801 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/19043 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2924/00012 , H01L2224/37099
摘要： A semiconductor package is disclosed. The package includes a leadframe having drain, source and gate leads, a semiconductor die coupled to the leadframe, the semiconductor die having metalized source and gate areas separated by a passivation area, a patterned source connection coupling the source lead to the semiconductor die metalized source area, a patterned gate connection coupling the gate lead to the semiconductor die metalized gate area, a semiconductor die drain area coupled to the drain lead, and an encapsulant covering at least a portion of the semiconductor die and drain, source and gate leads.
摘要翻译：公开了一种半导体封装。封装包括具有漏极，源极和栅极引线的引线框架，耦合到引线框架的半导体管芯，半导体管芯具有被钝化区域分开的金属化源极和栅极区域，将源极引线耦合到半导体管芯金属化源极的图案化源极连接区域，将栅极引线耦合到半导体管芯金属化栅极区域的图案化栅极连接，耦合到漏极引线的半导体管芯漏极区域以及覆盖半导体管芯和漏极，源极和栅极引线的至少一部分的密封剂。 / p>

2. 发明申请

WO2009045342A1 SEMICONDUCTOR PACKAGE HAVING A BRIDGED PLATE INTERCONNECTION 审中-公开
标题翻译：具有桥接板互连的半导体封装
公开(公告)号：WO2009045342A1
公开(公告)日：2009-04-09
申请号：PCT/US2008/011202
申请日：2008-09-26
申请人： ALPHA AND OMEGA SEMICONDUCTOR LIMITED , SHI, Lei , SUN, Ming , LIU, Kai
发明人： SHI, Lei , SUN, Ming , LIU, Kai
IPC分类号： H01L23/495
CPC分类号： H01L23/49524 , H01L23/49562 , H01L24/37 , H01L24/40 , H01L24/48 , H01L24/73 , H01L2224/32245 , H01L2224/37011 , H01L2224/371 , H01L2224/40095 , H01L2224/40245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/73219 , H01L2224/73221 , H01L2224/73265 , H01L2224/83801 , H01L2224/84801 , H01L2924/00014 , H01L2924/01006 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package is disclosed. The package includes a leadframe having drain, source and gate leads, and a semiconductor die coupled to the leadframe, the semiconductor die having a plurality of metalized source contacts. A bridged source plate interconnection has a bridge portion, valley portions disposed on either side of the bridge portion, plane portions disposed on either side of the valley portions and the bridge portion; and a connection portion depending from one of the plane portions, the bridged source plate interconnection connecting the source lead with the plurality of metalized source contacts. The bridge portion is disposed in a plane above the plane of the valley portions while the plane portions are disposed in a plane intermediate the plane of the bridge portion and the plane of the valley portions.
摘要翻译：公开了半导体封装。封装包括具有漏极，源极和栅极引线的引线框架以及耦合到引线框架的半导体管芯，该半导体管芯具有多个金属化源极触点。桥接源极板互连具有桥接部分，设置在桥接部分的任一侧上的谷部分，设置在谷部分和桥部分两侧的平面部分; 以及从所述平面部分之一悬垂的连接部分，所述桥接源极板互连件将所述源极引线与所述多个金属化源极触点连接。桥面部分设置在平坦部分的平面上方的平面中，而平面部分设置在桥接部分的平面和谷部的平面之间的平面中。

3. 发明申请

WO2008137001A2 SEMICONDUCTOR PACKAGE HAVING DIMPLED PLATE INTERCONNECTIONS 审中-公开
标题翻译：具有切割板互连的半导体封装
公开(公告)号：WO2008137001A2
公开(公告)日：2008-11-13
申请号：PCT/US2008/005563
申请日：2008-04-30
申请人： ALPHA & OMEGA SEMICONDUCTOR LIMITED , SUN, Ming , SHI, Lei , LIU, Kai
发明人： SUN, Ming , SHI, Lei , LIU, Kai
IPC分类号： H01L23/48
CPC分类号： H01L23/49524 , H01L23/49562 , H01L24/37 , H01L24/40 , H01L24/41 , H01L2224/32245 , H01L2224/37011 , H01L2224/4007 , H01L2224/40095 , H01L2224/40245 , H01L2224/40249 , H01L2224/4103 , H01L2224/73265 , H01L2224/83801 , H01L2224/84801 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01047 , H01L2924/01055 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2924/00012 , H01L2224/37099
摘要： A semiconductor package is disclosed. The package includes a leadframe having drain, source and gate leads, a semiconductor die coupled to the leadframe, the semiconductor die having a plurality of metalized source areas and a metalized gate area, a patterned source connection having a plurality of dimples formed thereon coupling the source lead to the semiconductor die metalized source areas, a patterned gate connection having a dimple formed thereon coupling the gate lead to the semiconductor die metalized gate area, a semiconductor die drain area coupled to the drain lead, and an encapsulant covering at least a portion of the semiconductor die and drain, source and gate leads.
摘要翻译：公开了半导体封装。封装包括具有漏极，源极和栅极引线的引线框架，耦合到引线框架的半导体管芯，具有多个金属化源极区域和金属化栅极区域的半导体管芯，具有形成在其上的多个凹坑的图案化源极连接，源极引导到半导体芯片金属化源极区域，具有形成在其上的凹坑的图案化栅极连接将栅极引线耦合到半导体管芯金属化栅极区域，耦合到漏极引线的半导体管芯漏极区域和覆盖至少一部分的密封剂的半导体管芯和漏极，源极和栅极引线。

4. 发明申请

WO2021236528A1 DUAL-MODE MULTI-CONJUGATE FILTER BASED ON DIFFERENT VOLTAGE DRIVEN SCHEMES 审中-公开
公开(公告)号：WO2021236528A1
公开(公告)日：2021-11-25
申请号：PCT/US2021/032781
申请日：2021-05-17
申请人： CHEMIMAGE CORPORATION , SHI, Lei , VENTOURIS, George , NELSON, Matthew, P. , TREADO, Patrick, J.
发明人： SHI, Lei , VENTOURIS, George , NELSON, Matthew, P. , TREADO, Patrick, J.
IPC分类号： G02F1/13 , G02F1/133 , G02F1/1337 , G02F1/1347 , G02F1/139
摘要： A multi-conjugate filter (MCF) can be operated in both a single bandpass mode and a multiple bandpass mode. By applying different voltages to different channels of a MCF, the MCF can be used to filter light into (1) a single narrow spectral output or (2) a broad ranged "white light" spectral output.

5. 发明申请

WO2012126379A1 THREE-DIMENSIONAL SYSTEM-LEVEL PACKAGING METHODS AND STRUCTURES 审中-公开
标题翻译：三维系统级包装方法和结构
公开(公告)号：WO2012126379A1
公开(公告)日：2012-09-27
申请号：PCT/CN2012/072772
申请日：2012-03-22
申请人： NANTONG FUJITSU MICROELECTRONICS CO., LTD. , TAO, Yujuan , SHI, Lei , WANG, Honghui
发明人： TAO, Yujuan , SHI, Lei , WANG, Honghui
IPC分类号： H01L25/00 , H01L23/485 , H01L21/60
CPC分类号： H01L23/485 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/80 , H01L24/82 , H01L25/00 , H01L2224/04105 , H01L2224/12105 , H01L2224/131 , H01L2224/13111 , H01L2224/24195 , H01L2224/32145 , H01L2224/32225 , H01L2224/73267 , H01L2224/92244 , H01L2924/00013 , H01L2924/014 , H01L2924/19105 , H05K1/185 , H01L2924/00014 , H01L2224/29099 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29599
摘要： A 3D system-level packaging method includes providing a packaging substrate (101), forming a glue layer (102) on the substrate (101), and attaching a first chip layer at an opposite side of a functional surface of the first chip layer on the packaging substrate (101) through the glue layer (102). The method also includes forming a first sealant layer on the packaging substrate (101) at a same side attached with the first chip layer and exposing bonding pads of the first chip layer. The method also includes forming first vias in the first sealant layer, forming first vertical metal wiring in the first vias, and forming a first horizontal wiring layer on the sealant layer interconnecting the first chip layer and the first vertical metal wiring. Further, the method includes forming a plurality of package layers on the first sealant layer, wherein each of the plurality of package layers includes a chip layer, a sealant layer covering the chip layer, and vertical metal wiring and a horizontal wiring layer (123) interconnecting adjacent package layers. 3D system-level packaging structures are also provided.
摘要翻译： 3D系统级封装方法包括提供封装衬底（101），在衬底（101）上形成胶层（102），以及将第一芯片层的功能表面的相反侧的第一芯片层与所述包装基板（101）穿过所述胶层（102）。该方法还包括在与第一芯片层相连的同一侧在封装衬底（101）上形成第一密封剂层并且暴露第一芯片层的焊盘。该方法还包括在第一密封剂层中形成第一通孔，在第一通孔中形成第一垂直金属布线，以及在互连第一芯片层和第一垂直金属布线的密封剂层上形成第一水平布线层。此外，该方法包括在第一密封剂层上形成多个封装层，其中多个封装层中的每一个包括芯片层，覆盖芯片层的密封剂层和垂直金属布线以及水平布线层（123）互连相邻的封装层。还提供了3D系统级封装结构。

6. 发明申请

WO2012126375A1 FAN-OUT HIGH-DENSITY PACKAGING METHODS AND STRUCTURES 审中-公开
标题翻译： FAN-OUT高密度包装方法和结构
公开(公告)号：WO2012126375A1
公开(公告)日：2012-09-27
申请号：PCT/CN2012/072766
申请日：2012-03-22
申请人： NANTONG FUJITSU MICROELECTRONICS CO., LTD. , TAO, Yujuan , SHI, Lei
发明人： TAO, Yujuan , SHI, Lei
IPC分类号： H01L21/50 , H01L25/00 , H01L21/56 , H01L23/31 , H01L23/52
CPC分类号： H01L23/49822 , H01L21/50 , H01L21/563 , H01L21/568 , H01L23/3128 , H01L23/3142 , H01L23/49816 , H01L23/49894 , H01L23/5389 , H01L24/23 , H01L24/24 , H01L24/25 , H01L24/82 , H01L2224/16225 , H01L2224/24226 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73204 , H01L2224/73267 , H01L2224/81005 , H01L2224/85005 , H01L2924/10253 , H01L2924/15311 , H01L2924/15788 , H01L2924/181 , H01L2924/19105 , H01L2924/30107 , H05K1/0306 , H05K1/111 , H05K1/181 , H05K1/185 , H05K2201/0154 , H05K2201/0195 , H05K2201/10674 , H01L2924/00 , H01L2924/00012
摘要： A fan-out high-density packaging method includes providing a packaging substrate, forming a stripping film on the packaging substrate, and forming a first protection layer on the stripping film and pre-designed photolithography pattern openings on the first protection layer. The method also includes forming a metal redistribution layer on the surface of the first protection layer and in the photolithography pattern openings, forming a second protection layer on the first protection layer and partially exposing the metal redistribution layer, and forming at least one package layer on the second protection layer. Each of at least one package layer includes a straight mounting layer, a sealant layer, and a wiring layer formed in sequence, and the package layer connects the metal redistribution layer through the wiring layer. Further, the method includes forming at least one top-level package layer on top of the at least one package layer, removing the packaging substrate and the stripping film to expose the metal redistribution layer in the first protection layer, and planting metal solder balls on the exposed metal redistribution layer.
摘要翻译：扇出式高密度封装方法包括提供封装衬底，在封装衬底上形成剥离膜，以及在剥离膜上形成第一保护层和在第一保护层上形成预先设计的光刻图案孔。该方法还包括在第一保护层的表面上和在光刻图案开口中形成金属再分布层，在第一保护层上形成第二保护层，并部分地暴露金属再分布层，并且形成至少一个封装层第二保护层。至少一个封装层中的每一个包括依次形成的直的安装层，密封剂层和布线层，并且封装层通过布线层连接金属再分配层。此外，该方法包括在至少一个封装层的顶部上形成至少一个顶层封装层，去除封装衬底和剥离膜以暴露第一保护层中的金属再分配层，并将金属焊球放置在暴露的金属再分配层。

7. 发明申请

WO2012042361A1 METHOD AND SYSTEM FOR PROVIDING PRESENCE SERVICE 审中-公开
标题翻译：提供存在服务的方法和系统
公开(公告)号：WO2012042361A1
公开(公告)日：2012-04-05
申请号：PCT/IB2011/002296
申请日：2011-08-24
申请人： ALCATEL LUCENT , SHI, Lei
发明人： SHI, Lei
IPC分类号： H04W8/18 , H04L12/16
CPC分类号： H04L67/26 , H04W4/60 , H04W8/10 , H04W80/04 , H04W84/045
摘要： The present invention discloses a method for providing presence service comprising: Femto directly sends acquired presence events to a presence server; the presence server converts the received presence events to corresponding presence information; a watcher sends a subscription request for presence information to the presence server; and the presence server sends the presence information to the watcher according to the subscription request for presence information. The present invention also discloses a system for providing presence service comprising: Femto, for directly sending acquired presence events to a presence server; the presence server, for converting the received presence events to corresponding presence information, receiving subscription requests for presence information sent by a watcher, and sending the presence information to the watcher according to the subscription requests for presence information; a watcher sends a subscription request for presence information to the presence server; and the presence server transmits the presence information to the watcher according to the subscription request for presence information. Since the presence events are directly sent to the presence server without passing the Femto gateway, the load of the Femto gateway is efficiently reduced and the operating efficiency thereof is thereby increased.
摘要翻译：本发明公开了一种用于提供现场服务的方法，包括：毫微微直接将获取的存在事件发送到在场服务器; 存在服务器将接收到的存在事件转换为相应的存在信息; 观察者向呈现服务器发送呈现信息的订阅请求; 并且存在服务器根据对存在信息的订阅请求向观察者发送呈现信息。本发明还公开了一种用于提供在场服务的系统，包括：用于将所获取的存在事件直接发送到在场服务器的毫微微; 存在服务器，用于将接收到的存在事件转换为对应的呈现信息，接收由观察者发送的呈现信息的订阅请求，以及根据对存在信息的订阅请求向观察者发送呈现信息; 观察者向呈现服务器发送呈现信息的订阅请求; 并且存在服务器根据存在信息的订阅请求向观察者发送呈现信息。由于存在事件直接发送到存在服务器而不通过毫微微网关，所以有效地降低了毫微微网关的负载，从而提高了其操作效率。

8. 发明申请

WO2012037810A1 WIDEBAND DUAL-POLARIZED RADIATION ELEMENT AND ANTENNA OF SAME 审中-公开
标题翻译：宽带双极化辐射元件和天线
公开(公告)号：WO2012037810A1
公开(公告)日：2012-03-29
申请号：PCT/CN2011/073205
申请日：2011-04-22
申请人： TONGYU COMMUNICATION INC. , HONG, Hezhi , SHI, Lei , FANG, Tieyong , WU, Yujiang , GAO, Zhuofeng , LIU, Muling , YE, Hai'ou
发明人： HONG, Hezhi , SHI, Lei , FANG, Tieyong , WU, Yujiang , GAO, Zhuofeng , LIU, Muling , YE, Hai'ou
IPC分类号： H01Q1/36 , H01Q5/01 , H01Q19/10 , H01Q21/26
CPC分类号： H01Q9/16 , H01Q1/246 , H01Q9/26 , H01Q19/106 , H01Q21/24 , H01Q21/30
摘要： A wideband dual-polarized radiation element (100) includes two pairs of cross polarized dipoles (11,12,13,14) and baluns (21,22,23,24), which correspondingly feed current to each dipole in balanced manner. Each dipole includes a pair of unit arms (11a and 11b, 12a and 12b, 13a and 13b, 14a and 14b) aligned on top of the corresponding balun. One end of each unit arm is connected on top of the balun, and the other end of one unit arm is bending inwards to form inward loaded line (61a, 62a, 63a, 64a), and the other unit arm is bending downwards to form downward loaded line(61b, 62b, 63b, 64b). An antenna (10) includes a metal reflector (20) and at least one wideband dual polarized radiation element, which has excellent radiation and polarization performance.
摘要翻译：宽带双极化辐射元件（100）包括两对交叉极化偶极子（11,12,13,14）和平衡不平衡变压器（21,22,23,24），其相应地以平衡的方式将电流馈送到每个偶极子。每个偶极子包括在对应的平衡 - 不平衡转换器的顶部上对准的一对单元臂（11a和11b，12a和12b，13a和13b，14a和14b）。每个单元臂的一端连接在平衡 - 不平衡转换器的上面，一个单元臂的另一端向内弯曲，形成向内的负载线（61a，62a，63a，64a），另一个单元臂向下弯曲形成向下装载线（61b，62b，63b，64b）。天线（10）包括金属反射器（20）和至少一个具有优异的辐射和极化性能的宽带双极化辐射元件。

9. 发明申请

WO2010036998A2 INDOLE AND INDOLINE DERIVATIVES AND METHODS OF USE THEREOF 审中-公开
标题翻译：吲哚和吲哚衍生物及其使用方法
公开(公告)号：WO2010036998A2
公开(公告)日：2010-04-01
申请号：PCT/US2009/058553
申请日：2009-09-28
申请人： ABBOTT LABORATORIES , SCHRIMPF, Michael R. , LEE, Chih-Hung , LI, Tao , GFESSER, Gregory A. , MORTELL, Kathleen H. , FAGHIH, Ramin , NERSESIAN, Diana L. , SIPPY, Kevin B. , BUNNELLE, William H. , SCANIO, Marc , SHI, Lei , GOPALAKRISHNAN, Murali , DONNELLY-ROBERTS, Diana , HU, Min
发明人： SCHRIMPF, Michael R. , LEE, Chih-Hung , LI, Tao , GFESSER, Gregory A. , MORTELL, Kathleen H. , FAGHIH, Ramin , NERSESIAN, Diana L. , SIPPY, Kevin B. , BUNNELLE, William H. , SCANIO, Marc , SHI, Lei , GOPALAKRISHNAN, Murali , DONNELLY-ROBERTS, Diana , HU, Min
IPC分类号： A61K31/439 , C12Q1/02 , C07D471/08
CPC分类号： G01N33/5058 , C07D471/18 , C07D487/10 , C07D487/18 , G01N33/6896 , G01N2800/28 , G01N2800/30
摘要： The present application relates to indole and indoline derivatives of formula (I), (II), (III), (IV), (V), or (VI) wherein a, R 1 , R 2 , R 3 , R 4 , R 5 , U, V, W, X, Y, and Z are as defined in the specification. The present application also relates to compositions comprising such compounds, and methods of treating disease conditions using such compounds and compositions, and methods for identifying such compounds.
摘要翻译：本申请涉及式（I），（II），（III），（IV），（V）或（VI）的吲哚和二氢吲哚衍生物，其中a，R1，R2，R3，R4，R5， V，W，X，Y和Z如说明书中所定义。本申请还涉及包含这些化合物的组合物，以及使用这些化合物和组合物治疗疾病状况的方法，以及鉴定这些化合物的方法。

10. 发明申请

WO2010009584A1 METHOD AND SYSTEM FOR SMART ADDRESS ASSIGNMENT BASED ON SERIAL BUS 审中-公开
标题翻译：基于串行总线的智能地址分配方法与系统
公开(公告)号：WO2010009584A1
公开(公告)日：2010-01-28
申请号：PCT/CN2008/001814
申请日：2008-10-29
申请人： JOHNSON CONTROLS TECHNOLOGY COMPANY , JOHNSON CONTROLS BUILDING EFFICIENCY TECHNOLOGY (WUXI) COMPANY, LTD , LUO Xi , XU, Hongchen , ZHANG, Yunfeng , SHI, Lei , ZHANG, Zhifeng , LIU, Yuanhui
发明人： LUO Xi , XU, Hongchen , ZHANG, Yunfeng , SHI, Lei , ZHANG, Zhifeng , LIU, Yuanhui
IPC分类号： H04L29/02
CPC分类号： H04L12/403 , H04L12/40019 , H04L29/12254 , H04L61/2038
摘要： The invention provides a system for a smart address assignment. The system includes: a host, including an MCU controller which executes address assignment function, a communication module, a memory and an initialization switch; a slave, including an MCU controller which executes address assignment function, a communication module, an electronic physical switch, a memory and an initialization switch; wherein the network is formed in the following manner: after being lead out from the host, the twisted pair lines are lead into the input terminal of the electronic physical switch of the first slave, then are lead from the output terminal of the electronic physical switch of the first slave to the input terminal of the electronic physical switch of the second slave.
摘要翻译：本发明提供了一种用于智能地址分配的系统。该系统包括：主机，包括执行地址分配功能的MCU控制器，通信模块，存储器和初始化开关; 从机，包括执行地址分配功能的MCU控制器，通信模块，电子物理交换机，存储器和初始化开关; 其中网络以如下方式形成：从主机引出之后，双绞线引导到第一从机的电子物理开关的输入端，然后从电子物理开关的输出端引出的第一从机到第二从机的电子物理开关的输入端。

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