专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

2. 发明专利

JP2002026219A SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2002026219A
公开(公告)日：2002-01-25
申请号：JP2000206748
申请日：2000-07-07
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： ITO FUJIO , KAMEOKA AKIHIKO , SUZUKI HIROMICHI , NAGAI AKIRA , KUSUKAWA JUNPEI , TSUGANE MASAYOSHI
IPC分类号： H01L23/28 , H01L23/29 , H01L23/50
摘要： PROBLEM TO BE SOLVED: To prevent migration of lead material, in a semiconductor device of a plastic package type having a heat spreader. SOLUTION: In the semiconductor device 1 of the plastic package type including the heat spreader 5, leads 3 are connected with the heat spreader 5 via an adhesive agent layer 9. A plating layer 10 is formed on the surface of the lead 3 in such a manner that a distance d is ensured from the upper surface of the adhesive agent layer 9.

3. 发明专利

JP2000156419A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JP2000156419A
公开(公告)日：2000-06-06
申请号：JP25086598
申请日：1998-09-04
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： ASAKURA HISAO , TADAKI YOSHITAKA , SEKIGUCHI TOSHIHIRO , NAGAI AKIRA , MIYAMOTO MASABUMI , NAKAMURA MASAYUKI , MIYATAKE SHINICHI , SUZUKI SHINKO , HIYOUMA MASAHIRO
IPC分类号： H01L21/8234 , H01L21/265 , H01L21/336 , H01L21/8238 , H01L21/8242 , H01L27/088 , H01L27/10 , H01L27/108 , H01L29/49
摘要： PROBLEM TO BE SOLVED: To raise the integration degree of elements without causing the degradation of the performance of a MOS field-effect transistor. SOLUTION: This manufacturing method is a method for manufacturing a MISFET(Metal Insulator Semiconductor Field-Effect Transistor) of a structure, wherein in the case where impurities for short-channel effect inhibition are doped in a semiconductor substrate 1 obliquely to the main surface of the substrate 1, gate electrodes 3 and 3 adjacent to each other are arranged so that the impurities, which are doped in the substrate 1 from the direction intersecting the electrodes 3, are not doped between the electrodes 3 and 3 and the electrodes 3 and 3 are arranged so that a source region of the MISFET is arranged between the electrodes 3 and 3.

4. 发明专利

JP2000150878A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JP2000150878A
公开(公告)日：2000-05-30
申请号：JP32758798
申请日：1998-11-18
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： MIYAMOTO MASABUMI , ASAKURA HISAO , HIYOUMA MASAHIRO , SUZUKI NORIO , NAGAI AKIRA
IPC分类号： H01L21/76 , H01L21/8238 , H01L21/8242 , H01L27/092 , H01L27/108 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To prevent the characteristic degradation of a MISFET caused by unevenly distributing impurities in the silicon oxide film of an element separation groove and reducing the concentration at the end part of an active region, by performing the ion implantation of the impurities from a slanting direction onto the main surface of a semiconductor substrate where the element isolation groove is formed. SOLUTION: The ion implantation of p-type impurities such as B(boron) for forming a channel region is made in the memory cell formation region of a semiconductor substrate 1 and another part (p-type well formation region) of a periphery circuit formation region. The p-type impurities are implanted from a slanting direction onto the main surface of the semiconductor substrate 1. For example, the semiconductor substrate (wafer) 1 is rotated by 90 degrees within a horizontal surface. An incident angle θ of the p-type impurities should be set within approximately 15-60 degrees, and is preferably set to approximately 45 degrees, thus suppressing the uneven distribution of the p-type impurities for forming the channel region, and the drop of a threshold voltage caused by reducing the concentration of the impurities near an element isolation region.

5. 发明专利

JP2000243929A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JP2000243929A
公开(公告)日：2000-09-08
申请号：JP4210899
申请日：1999-02-19
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： OYU SHIZUNORI , MIURA MASASHI , NAGAI AKIRA
IPC分类号： H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To modify the electric field in the semiconductor region of a memory- cell selection transistor. SOLUTION: In a semiconductor substrate 1, a trench 15 is formed at a position underneath a contact hole 14A for connecting to a capacitor. An insulating film 16 is formed on the side plane of the trench 15. By forming an n+ semiconductor region 9b of a memory-cell selection transistor Qs in the deep position of the semiconductor substrate 1, a gate electrode 7A and the n+ semiconductor region 9b can be separated without increasing occupation area of the device element.

6. 发明授权

US6423571B2 Method of making a semiconductor device having a stress relieving mechanism 失效
标题翻译：制造具有应力消除机构的半导体器件的方法
公开(公告)号：US6423571B2
公开(公告)日：2002-07-23
申请号：US88437801
申请日：2001-06-20
申请人： HITACHI LTD
发明人： OGINO MASAHIKO , NAGAI AKIRA , EGUCHI SHUJI , ISHII TOSHIAKI , SEGAWA MASANORI , AKAHOSHI HARUO , TAKAHASHI AKIO , MIWA TAKAO , TANAKA NAOTAKA , ANJOU ICHIROU
IPC分类号： H01L23/498 , H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L23/49816 , H01L23/49827 , H01L2924/0002 , H01L2924/30107 , H01L2924/3011 , H01L2924/00
摘要： A method of forming a semiconductor device having a multi-layered wiring structure that includes a conductor layer to be electrically connected to a packaging substrate, with the multi-layered wiring structure being provided on a circuit formation surface of a semiconductor chip. Ball-like terminals are formed, disposed in a grid array on the surface of the multi-layered wiring structure on the packaging substrate side. The multi-layered wiring structure is formed to include a buffer layer for relieving a thermal stress provided between the semiconductor chip and the packaging substrate, due to the packaging procedure. In the semiconductor device formed, the wiring distance is shorter than that of a conventional semiconductor device, so that an inductance component becomes smaller, to thereby increase signal speed. The distance between a ground layer and a power supply layer is shortened, to reduce noise produced upon operation, and also a thermal stress upon packaging is relieved by the buffer layer of the multi-layered wiring structure, resulting in improved connection reliability, and the number of terminals per unit can be increased, because of elimination of wire bonding. The buffer layer can be made of an elastomer, and can have a modulus of elasticity of 10 kg/mm2 or less.
摘要翻译：一种形成具有多层布线结构的半导体器件的方法，所述多层布线结构包括导体层，以与所述封装衬底电连接，所述多层布线结构设置在所述半导体芯片的电路形成表面上。在包装基板一侧的多层布线结构的表面上形成有格子状的球状端子。多层布线结构形成为包括用于缓解由于包装过程而在半导体芯片和封装基板之间提供的热应力的缓冲层。在形成的半导体器件中，布线距离比常规半导体器件的布线距离短，使得电感成分变小，从而提高信号速度。接地层和电源层之间的距离缩短，以减少操作时产生的噪声，并且多层布线结构的缓冲层也减轻了包装上的热应力，从而提高了连接可靠性，并且由于消除引线键合，可以增加每单位端子数量。缓冲层可以由弹性体制成，并且可以具有10kg / mm 2或更小的弹性模量。

7. 发明专利

SG75846A1 Semiconductor device and wiring tape for semiconductor device 未知
公开(公告)号：SG75846A1
公开(公告)日：2000-10-24
申请号：SG1998001200
申请日：1998-06-05
申请人： HITACHI LTD , HITACHI CABLE
发明人： OGINO MASAHIKO , SHIRAKATA SHUJI EGUHCI , NAGAI AKIRA , UENO TAKUMI , SEGAWA MASANORI , KOKAKU HIROYOSHI , ISHII TOSHIAKI , ANJO ICHIRO , NISHIMURA ASAO , MIYAZAKI CHUICHI , MITA MAMORU , OKABE NORIO
IPC分类号： H01L23/12 , H01L23/31 , H01L23/495 , H01L23/498
摘要： A semiconductor device has a three-layered buffer layer comprising core layer 1 having interconnected foams such as a three-dimensional reticular structure and adhesive layers 2 provided on both sides of the core layer 1 as a stress buffer layer between semiconductor chip 5 and wiring 4 to lessen thermal stress generated between the semiconductor device and the package substrate. The thickness ratio of core layer 1 to total buffer layer is at least 0.2. The production process can be simplified by using such a buffer layer, thereby improving the mass production capacity and enhancing the package reliability.

8. 发明专利

DE69406390T2 未知
公开(公告)号：DE69406390T2
公开(公告)日：1998-05-20
申请号：DE69406390
申请日：1994-07-07
申请人： HITACHI LTD
发明人： NAGAI AKIRA , OGATA MASATSUGU
IPC分类号： B32B17/04 , B32B5/26 , B32B27/12 , C08J5/24 , H01L23/14 , H05K1/03 , H05K3/46

9. 发明专利

DE3853868D1 未知
公开(公告)号：DE3853868D1
公开(公告)日：1995-06-29
申请号：DE3853868
申请日：1988-11-04
申请人： HITACHI LTD
发明人： SUGAWARA KATUO , TAKAHASHI AKIO , KATAGIRI JUNICHI , NAGAI AKIRA , ONO MASAHIRO , NARAHARA TOSHIKAZU
IPC分类号： C08G59/34 , B32B27/04 , B32B27/38 , C08F279/02 , C08G59/00 , C08G59/32 , C08G59/40 , C08J5/24 , C08L25/00 , C08L25/18 , C08L63/00 , C08L63/08 , H05K1/03 , B32B27/28
摘要： The present invention provide a thermosetting resin composition comprising (a) a prepolymer of a poly (p-hydroxystyrene) derivative represented by the general formula wherein A is a halogen group, R1 is an alkenyl or alkenoyl group of 2 to 4 carbon atoms, m denotes a number of 1 to 4 and n denotes a number of 1 to 100, (b) an epoxy-modified polybutadiene, and (c) an aromatic maleimide compound, and a prepreg and a laminated sheet which use said resin composition. s

10. 发明专利

DE3750641T2 未知
公开(公告)号：DE3750641T2
公开(公告)日：1995-04-06
申请号：DE3750641
申请日：1987-02-13
申请人： HITACHI LTD
发明人： KATAGIRI JUNICHI , NAGAI AKIRA , TAWARA KEIKO , TAKAHASHI AKIO , NARAHARA TOSHIKAZU , HIRAGA RYO , WAJIMA MOTOYO
IPC分类号： C08L25/04 , C08F8/00 , C08F12/22 , C08F290/12 , C08F299/00 , C08G59/34 , C08L63/08 , H05K1/03 , C08F12/14 , C08L25/18 , C08L15/00 , C08L63/10
摘要： A thermosetting resin composition comprising a special poly(p-hydroxystyrene) derivative resin and a radical polymerization initiator, and if necessary an epoxy modified polybutadiene, can provide prepregs and laminates having a low dielectric constant, a shorter signalling delay time, good heat resistance and flame retardancy and thus being suitable for producing multilayer printed circuit boards.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式