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1. 发明授权

US6423571B2 Method of making a semiconductor device having a stress relieving mechanism 失效
标题翻译：制造具有应力消除机构的半导体器件的方法
公开(公告)号：US6423571B2
公开(公告)日：2002-07-23
申请号：US88437801
申请日：2001-06-20
申请人： HITACHI LTD
发明人： OGINO MASAHIKO , NAGAI AKIRA , EGUCHI SHUJI , ISHII TOSHIAKI , SEGAWA MASANORI , AKAHOSHI HARUO , TAKAHASHI AKIO , MIWA TAKAO , TANAKA NAOTAKA , ANJOU ICHIROU
IPC分类号： H01L23/498 , H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L23/49816 , H01L23/49827 , H01L2924/0002 , H01L2924/30107 , H01L2924/3011 , H01L2924/00
摘要： A method of forming a semiconductor device having a multi-layered wiring structure that includes a conductor layer to be electrically connected to a packaging substrate, with the multi-layered wiring structure being provided on a circuit formation surface of a semiconductor chip. Ball-like terminals are formed, disposed in a grid array on the surface of the multi-layered wiring structure on the packaging substrate side. The multi-layered wiring structure is formed to include a buffer layer for relieving a thermal stress provided between the semiconductor chip and the packaging substrate, due to the packaging procedure. In the semiconductor device formed, the wiring distance is shorter than that of a conventional semiconductor device, so that an inductance component becomes smaller, to thereby increase signal speed. The distance between a ground layer and a power supply layer is shortened, to reduce noise produced upon operation, and also a thermal stress upon packaging is relieved by the buffer layer of the multi-layered wiring structure, resulting in improved connection reliability, and the number of terminals per unit can be increased, because of elimination of wire bonding. The buffer layer can be made of an elastomer, and can have a modulus of elasticity of 10 kg/mm2 or less.
摘要翻译：一种形成具有多层布线结构的半导体器件的方法，所述多层布线结构包括导体层，以与所述封装衬底电连接，所述多层布线结构设置在所述半导体芯片的电路形成表面上。在包装基板一侧的多层布线结构的表面上形成有格子状的球状端子。多层布线结构形成为包括用于缓解由于包装过程而在半导体芯片和封装基板之间提供的热应力的缓冲层。在形成的半导体器件中，布线距离比常规半导体器件的布线距离短，使得电感成分变小，从而提高信号速度。接地层和电源层之间的距离缩短，以减少操作时产生的噪声，并且多层布线结构的缓冲层也减轻了包装上的热应力，从而提高了连接可靠性，并且由于消除引线键合，可以增加每单位端子数量。缓冲层可以由弹性体制成，并且可以具有10kg / mm 2或更小的弹性模量。

2. 发明专利

MY119817A SEMICONDUCTOR DEVICE HAVING A POROUS BUFFER LAYER FOR SEMICONDUCTOR DEVICE 未知
公开(公告)号：MY119817A
公开(公告)日：2005-07-29
申请号：MYPI9802523
申请日：1998-06-05
申请人： HITACHI CABLE , HITACHI LTD
发明人： OGINO MASAHIKO , MIYAZAKI CHUICHI , MITA MAMORU , OKABE NORIO , EGUCHI SHUJI , NAGAI AKIRA , UENO TAKUMI , SEGAWA MASANORI , KOKAKU HIROYOSHI , ISHII TOSHIAKI , ANJOH ICHIRO , NISHIMURA ASAO
IPC分类号： H01L23/12 , H01L23/31 , H01L23/495 , H01L23/498
摘要： IN A SEMICONDUCTOR DEVICE HAVING A THREE-LAYERED BUFFER LAYER COMPRISING CORE LAYER (1) HAVING INTERCONNECTED FOAMS SUCH AS A THREE-DIMENSIONAL RETICULAR STRUCTURE AND ADHESIVE LAYERS (2) PROVIDED ON BOTH SIDES OF THE CORE LAYER AS A STRESS BUFFER LAYER BETWEEN SEMICONDUCTOR CHIP (5) AND WIRING (4) TO LESSEN A THERMAL STRESS GENERATED BETWEEN THE SEMICONDUCTOR DEVICE AND THE PACKAGE SUBSTRATE, WHERE A THICKNESS RATIO OF CORE LAYER (1) TO TOTAL BUFFER LAYER IS AT LEAST 0.2, THE PRODUCTION PROCESS CAN BE SIMPLIFIED BY USING SUCH A BUFFER LAYER, THEREBY IMPROVING THE MASS PRODUCTION CAPACITY AND ENHANCING THE PACKAGE RELIABILITY.

3. 发明专利

SG75846A1 Semiconductor device and wiring tape for semiconductor device 未知
公开(公告)号：SG75846A1
公开(公告)日：2000-10-24
申请号：SG1998001200
申请日：1998-06-05
申请人： HITACHI LTD , HITACHI CABLE
发明人： OGINO MASAHIKO , SHIRAKATA SHUJI EGUHCI , NAGAI AKIRA , UENO TAKUMI , SEGAWA MASANORI , KOKAKU HIROYOSHI , ISHII TOSHIAKI , ANJO ICHIRO , NISHIMURA ASAO , MIYAZAKI CHUICHI , MITA MAMORU , OKABE NORIO
IPC分类号： H01L23/12 , H01L23/31 , H01L23/495 , H01L23/498
摘要： A semiconductor device has a three-layered buffer layer comprising core layer 1 having interconnected foams such as a three-dimensional reticular structure and adhesive layers 2 provided on both sides of the core layer 1 as a stress buffer layer between semiconductor chip 5 and wiring 4 to lessen thermal stress generated between the semiconductor device and the package substrate. The thickness ratio of core layer 1 to total buffer layer is at least 0.2. The production process can be simplified by using such a buffer layer, thereby improving the mass production capacity and enhancing the package reliability.

4. 发明专利

DE69838696T2 未知
公开(公告)号：DE69838696T2
公开(公告)日：2008-03-06
申请号：DE69838696
申请日：1998-06-02
申请人： HITACHI LTD , HITACHI CABLE
发明人： OGINO MASAHIKO , EGUCHI SHUJI , NAGAI AKIRA , UENO TAKUMI , SEGAWA MASANORI , KOKAKU HIROYOSHI , ISHII TOSHIAKI , ANJO ICHIRO , NISHIMURA ASAO , MIYAZAKI CHUICHI , MITA MAMORU , OKABE NORIO
IPC分类号： H01L23/12 , H01L23/495 , H01L21/48 , H01L21/58 , H01L21/60 , H01L23/31 , H01L23/498
摘要： A semiconductor device has a three-layered buffer layer comprising core layer 1 having interconnected foams such as a three-dimensional reticular structure and adhesive layers 2 provided on both sides of the core layer 1 as a stress buffer layer between semiconductor chip 5 and wiring 4 to lessen thermal stress generated between the semiconductor device and the package substrate. The thickness ratio of core layer 1 to total buffer layer is at least 0.2. The production process can be simplified by using such a buffer layer, thereby improving the mass production capacity and enhancing the package reliability.

5. 发明专利

DE69838696D1 未知
公开(公告)号：DE69838696D1
公开(公告)日：2007-12-27
申请号：DE69838696
申请日：1998-06-02
申请人： HITACHI LTD , HITACHI CABLE
发明人： OGINO MASAHIKO , EGUCHI SHUJI , NAGAI AKIRA , UENO TAKUMI , SEGAWA MASANORI , KOKAKU HIROYOSHI , ISHII TOSHIAKI , ANJO ICHIRO , NISHIMURA ASAO , MIYAZAKI CHUICHI , MITA MAMORU , OKABE NORIO
IPC分类号： H01L23/12 , H01L23/495 , H01L21/48 , H01L21/58 , H01L21/60 , H01L23/31 , H01L23/498
摘要： A semiconductor device has a three-layered buffer layer comprising core layer 1 having interconnected foams such as a three-dimensional reticular structure and adhesive layers 2 provided on both sides of the core layer 1 as a stress buffer layer between semiconductor chip 5 and wiring 4 to lessen thermal stress generated between the semiconductor device and the package substrate. The thickness ratio of core layer 1 to total buffer layer is at least 0.2. The production process can be simplified by using such a buffer layer, thereby improving the mass production capacity and enhancing the package reliability.

6. 发明专利

MY125437A SEMICONDUCTOR DEVICE, SEMICONDUCTOR WAFER, SEMICONDUCTOR MODULE AND A METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 未知
公开(公告)号：MY125437A
公开(公告)日：2006-08-30
申请号：MYPI9904556
申请日：1999-10-21
申请人： HITACHI LTD
发明人： OGINO MASAHIKO , NISHIMURA ASAO , ANJOH ICHIRO , UENO TAKUMI , EGUCHI SYUJI , NAGAI AKIRA , SATOH TOSHIYA , ISHII TOSHIAKI , KOKAKU HIROYOSHI , SEGAWA MASANORI , TSUYUNO NOBUTAKE
IPC分类号： H01L21/60 , H01L23/12 , H01L21/301 , H01L21/46 , H01L21/48 , H01L21/50 , H01L23/28 , H01L23/31 , H01L23/50 , H01L23/52 , H01L29/40
摘要： SEMICONDUCTOR DEVICES, SEMICONDUCTOR WAFERS, AND REMICONDUCTOR MODULES ARE PROVIDED: WHEREIN THE SEMICONDUCTOR DEVICE HAS A SMALL WARP; DAMAGES AT CHIP EDGE AND CRACKS IN A DROPPING TEST ARE SCARCELY GENERATED; AND THE SEMICONDUCTOR DEVICE IS SUPERIOR IN MOUNTING RELIABILITY AND MASS PRODUCIBILITY. THE SEMICONDUCTOR DEVICE 17 COMPRISING: A SEMICONDUCTOR CHIP 64; A POROUS STRESS RELAXING LAYER 3 PROVIDED ON THE PLANE, WHEREON CIRCUITS AND ELECTRODES ARE FORMED, OF THE SEMICONDUCTOR CHIP; A CIRCUIT LAYER 2 PROVIDED ON THE STRESS RELAXING LAYER AND CONNECTED TO THE ELECTRODES; AND EXTERNAL TERMINALS 10 PROVIDED ON THE CIRCUIT LAYER; WHEREIN AN ORGANIC PROTECTING FILM 7 IS FORMED ON THE PLANE, OPPOSITE TO THE STRESS RELAXING LAYER, OF THE SEMICONDUCTOR CHIP, AND RESPECTIVE SIDE PLANES OF. THE STRESS RELAXING LAYER, THE SEMICONDUCTOR CHIP 6, AND THE PROTECTING FILM 7 ARE EXPOSED OUTSIDE ON A SAME PLANE.(FIG. 1)

7. 发明专利

JP2012094873A Bonding method and bonding material using metal particle 审中-公开
标题翻译：使用金属颗粒的粘合方法和粘合材料
公开(公告)号：JP2012094873A
公开(公告)日：2012-05-17
申请号：JP2011241832
申请日：2011-11-04
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： YASUDA YUSUKE , MORITA TOSHIAKI , IDE HIDEKAZU , HOZOJI HIROYUKI , ISHII TOSHIAKI
IPC分类号： H01L21/52 , C22C5/06 , H01L23/48 , H01L25/07 , H01L25/18
CPC分类号： B23K35/34 , B23K35/3612 , H01L23/3107 , H01L24/27 , H01L24/29 , H01L24/30 , H01L24/32 , H01L24/33 , H01L24/45 , H01L24/73 , H01L24/83 , H01L25/072 , H01L2224/04026 , H01L2224/05639 , H01L2224/2731 , H01L2224/29101 , H01L2224/29111 , H01L2224/29139 , H01L2224/2919 , H01L2224/29294 , H01L2224/29387 , H01L2224/29393 , H01L2224/30181 , H01L2224/32175 , H01L2224/32225 , H01L2224/32245 , H01L2224/33181 , H01L2224/45015 , H01L2224/45124 , H01L2224/45147 , H01L2224/48227 , H01L2224/48247 , H01L2224/48739 , H01L2224/48839 , H01L2224/73265 , H01L2224/83191 , H01L2224/83192 , H01L2224/83203 , H01L2224/83444 , H01L2224/83447 , H01L2224/83455 , H01L2224/8384 , H01L2224/83986 , H01L2224/85205 , H01L2224/8584 , H01L2924/00011 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01044 , H01L2924/01045 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01076 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/0541 , H01L2924/0665 , H01L2924/09701 , H01L2924/10253 , H01L2924/12041 , H01L2924/13091 , H01L2924/15747 , H01L2924/15787 , H01L2924/16195 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/19105 , H01L2924/19107 , H01L2924/00014 , H01L2924/2076 , H01L2924/00 , H01L2924/00012 , H01L2924/3512 , H01L2224/48 , H01L2224/83205
摘要： PROBLEM TO BE SOLVED: To provide a bonding material and a bonding method capable of realizing bonding by metallic bonding at a bonding interface at a lower temperature compared to the bonding material using a metal particle having an average particle diameter of 100 nm or the less.SOLUTION: A bonding material comprises: at least one or more of a metal particle precursor selected from particles of a metal oxide, a metal carbonate, and a metal carboxylate having an average particle diameter of 1 nm to 50 μm; and a reducing agent composed of an organic substance. In the bonding material the content of the metal particle precursor is more than 50 pts.mass and not more than 99 pts.mass per 100 pts.mass of the bonding material.
摘要翻译：解决的问题：提供一种接合材料和接合方法，该接合材料和接合方法与使用平均粒径为100nm的金属颗粒的接合材料相比，在较低温度下的接合界面处通过金属接合实现接合，或少了粘合材料包括：选自平均粒径为1nm至50μm的金属氧化物，金属碳酸盐和金属羧酸盐的颗粒中的至少一种或多种金属颗粒前体; 和由有机物构成的还原剂。在接合材料中，金属颗粒前体的含量比粘合材料的每100分钟大于50点，不大于99点。版权所有（C）2012，JPO＆INPIT

8. 发明专利

JP2012089893A Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：JP2012089893A
公开(公告)日：2012-05-10
申请号：JP2012022638
申请日：2012-02-06
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： SAKAMOTO MITSUZO , ISHII TOSHIAKI
IPC分类号： H01L25/07 , H01L25/18
CPC分类号： H01L25/072 , H01L23/49844 , H01L23/5383 , H01L23/5385 , H01L25/115 , H01L25/117 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2224/73253 , H01L2924/00014 , H01L2924/10272 , H01L2924/1033 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/13062 , H01L2924/13091 , H01L2924/15192 , H01L2924/3011 , H01L2924/00 , H01L2224/05599
摘要： PROBLEM TO BE SOLVED: To provide a power semiconductor device capable of achieving high breakdown voltage, low thermal resistance, low parasitic resistance, small size, and increasing current.SOLUTION: A power semiconductor device of the present invention comprises: a semiconductor chip that has a first semiconductor region of a first conductive type to which a first electrode is connected and a second semiconductor region of a second conductive type to which a second electrode is connected and in which a first electrode pad for the first electrode is provided on a primary surface of a semiconductor substrate in a region surrounded by a third semiconductor region of the first conductive type provided in the second semiconductor region; and a multilayer substrate having a first wiring layer and a second wiring layer for pulling out electrodes of the semiconductor chip. A first wiring layer portion for the first electrode provided in the opposite region to the region surrounded by the third semiconductor region on the primary surface of the semiconductor substrate and the first electrode pad are connected to the multilayer substrate by a conductive adhesive agent. The first wiring layer portion for the first electrode and the second wiring layer are connected by conductive through holes. The second wiring layer is extended outside the region opposite to the primary surface of the semiconductor substrate in the region surrounded by the third semiconductor region.
摘要翻译：要解决的问题：提供能够实现高击穿电压，低热阻，低寄生电阻，小尺寸和增加电流的功率半导体器件。解决方案：本发明的功率半导体器件包括：半导体芯片，其具有连接有第一电极的第一导电类型的第一半导体区域和具有第二导电类型的第二导电类型的第二半导体区域，电极被连接，并且其中用于第一电极的第一电极焊盘设置在由设置在第二半导体区域中的第一导电类型的第三半导体区域包围的区域中的半导体衬底的主表面上; 以及具有用于拉出半导体芯片的电极的第一布线层和第二布线层的多层基板。在与半导体衬底的主表面上的第三半导体区域围绕的区域的相对区域中设置的第一电极的第一电极层部分和第一电极焊盘通过导电粘合剂连接到多层衬底。用于第一电极和第二布线层的第一布线层部分通过导电通孔连接。在由第三半导体区域包围的区域中，第二布线层延伸到与半导体衬底的主表面相对的区域的外侧。版权所有（C）2012，JPO＆INPIT

9. 发明专利

JP2010056355A Transfer mold type electronic control device 有权
标题翻译：转印模型电子控制装置
公开(公告)号：JP2010056355A
公开(公告)日：2010-03-11
申请号：JP2008220683
申请日：2008-08-29
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： TSUYUNO ENJO , UCHIYAMA KAORU , HOZOJI HIROYUKI , TANABE ITARU , SHIGYO TOSHIKAZU , ISHII TOSHIAKI
IPC分类号： H01L25/00 , H01L23/28 , H01L23/29 , H01L23/31
CPC分类号： H01L2224/48091 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To provide a transfer mold type electronic control device of a compact size and high reliability capable of being built in a mechanical component. SOLUTION: In the electronic control device, a substrate mounted with an electronic component of a surface mounting type is transfer-molded. The transfer mold type electronic control device has two or more substrates, at least one of the substrates is double-side mounted, and the substrates are arranged by laminating with gaps, and the device has a supporting structure wherein an interval between the substrates is fixed constant. COPYRIGHT: (C)2010,JPO&INPIT

10. 发明专利

JP2010040992A Method of manufacturing electronic control device, its transfer molding equipment and electronic control device 审中-公开
标题翻译：制造电子控制装置的方法及其转印成型设备和电子控制装置
公开(公告)号：JP2010040992A
公开(公告)日：2010-02-18
申请号：JP2008205524
申请日：2008-08-08
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： ISHII TOSHIAKI , URUSHIBARA NORIMI , TAKASE KOSUKE
IPC分类号： H01L21/56
CPC分类号： H01L2224/48091 , H01L2224/48227 , H01L2224/4903 , H01L2924/181 , H01L2924/19105 , H01L2924/19107 , H01L2924/00012 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To prevent the damage to a connector and a connection part, and secure surface pressure between the connector and a molding die to prevent leakage of a resin, by lowering stress given to the connector and the connection part between the connector and an electronic circuit board, when molding, in a method of manufacturing an electronic control device. SOLUTION: The electronic control device includes the connector 3 having the electronic circuit board 2, a metal terminal 5 in which one end protrudes for connecting to an external electronic circuit, and the peripheral flange 7. The method of manufacturing the electronic control device has a step of arranging a whole of the electronic circuit board 2 and a part of the connector 3 within the molding dies 8a, 8b, and a step of integrally forming them with a thermosetting resin composition 4 by a low pressure transfer mold method. When integrally forming, while contacting one surface of the flange 7 to a wall surface around the one end opening of the molded product delivery side of the molding dies 8a, 8b, and applying pressing force to the flange 7 in a direction in parallel with a projection direction 6 of the metal terminal 5, the low pressure transfer mold method is performed. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了防止连接器和连接部件的损坏，并且通过降低连接器和连接部件之间的应力，可以确保连接器和成型模具之间的表面压力，以防止树脂泄漏连接器和电子电路板，当成型时，以电子控制装置的制造方法。解决方案：电子控制装置包括具有电子电路板2的连接器3，一个端部突出以连接到外部电子电路的金属端子5和外围凸缘7.制造电子控制的方法装置具有将整个电子电路板2和连接器3的一部分布置在模具8a，8b内的步骤，以及通过低压转移模具法与热固性树脂组合物4一体地形成的步骤。当将凸缘7的一个表面与成型模具8a，8b的模制产品出口侧的一个端部开口周围的壁表面接触一体地形成时，并且在与凸缘7平行的方向上向凸缘7施加压力金属端子5的突出方向6，执行低压转移模具法。版权所有（C）2010，JPO＆INPIT

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