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1. 发明申请

WO03063167A3 SYSTEM AND METHOD FOR PROGRAMMING ONO DUAL BIT MEMORY CELLS 审中-公开
标题翻译：用于编程双位存储器单元的系统和方法
公开(公告)号：WO03063167A3
公开(公告)日：2003-12-04
申请号：PCT/US0240775
申请日：2002-12-17
申请人： ADVANCED MICRO DEVICES INC
发明人： HAMILTON DARLENE , THURGATE TIMOTHY , WANG JANET S Y , HAN MICHAEL K , DERHACOBIAN NARBEH
IPC分类号： G11C16/02 , G11C11/56 , G11C16/04 , G11C16/10 , G11C16/34 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/3409 , G11C11/5657 , G11C11/5671 , G11C16/0475 , G11C16/10 , G11C16/3404 , G11C16/3436 , G11C16/3445
摘要： A system and methodology is provided for programming first bit (CO, C2, C4, C6) and second bit (C1, C3, C5, C7) of a memory array (68) of dual bit memory cells (10, 82, 84, 86, 88) at a substantially high delta VT. The substantially higher VT assures that the memory array (68) will maintain programmed data and erase data consistently after higher temperature stresses and/or custumer operation over substantial periods of time. At a substantially higher delta VT, programming of the first bit (C0, C2, C4, C6) of the memory cell (10, 82, 84, 86, 88) causes the second bit (C1, C3, C5, C7) to program harder and faster due to the shorter channel (8) length. Therefore, the present invention employs selected gate and drain voltages and programming pulse widths during programming of the first bit (C0, C2, C4, C6) and second bit (C1, C3, C5, C7) that assures a controlled first bit VT and slows down programming of the second bit (C1,C3, C5, C7). Furthermore, the selected programming parameters keep the programming times short without degrading charge loss.
摘要翻译：提供了一种系统和方法，用于对双位存储器单元（10,82,84,86）的存储器阵列（68）的第一位（CO，C2，C4，C6）和第二位（C1，C3，C5，C7） 86,88）处于基本上高的三角洲VT。基本上较高的VT确保存储器阵列（68）将在相当长的一段时间内在更高的温度应力和/或操作者操作之后保持编程的数据并且一致地擦除数据。在基本上较高的增量VT下，存储器单元（10,82,84,86,88）的第一位（C0，C2，C4，C6）的编程使第二位（C1，C3，C5，C7）由于短通道（8）的长度，程序越来越快。因此，本发明在第一位（C0，C2，C4，C6）和第二位（C1，C3，C5，C7）的编程期间采用选定的栅极和漏极电压和编程脉冲宽度，以确保受控的第一位VT和减慢第二位（C1，C3，C5，C7）的编程速度。此外，所选择的编程参数保持编程时间短而不降低电荷损耗。

2. 发明申请

WO02080181A3 I/O PARTITIONING SYSTEM AND METHODOLOGY TO REDUCE BAND-TO-BAND TUNNELING CURRENT DURING ERASE 审中-公开
标题翻译： I / O分区系统和方法，以减少擦除期间的带对带隧道电流
公开(公告)号：WO02080181A3
公开(公告)日：2003-01-09
申请号：PCT/US0143543
申请日：2001-11-14
申请人： ADVANCED MICRO DEVICES INC , FUJITSU LTD
发明人： BAUTISTA EDWARD V JR , KURIHARA KAZUHIRO , PAN FENG , LEE WENG FOOK , SUNKAVALLI RAVI , HAMILTON DARLENE
IPC分类号： G11C16/02 , G11C16/06 , G11C16/16 , G11C16/34 , G11C16/30
CPC分类号： G11C16/3445 , G11C16/16 , G11C16/344
摘要： A system (10a) is provided for reducing band-to-band tunneling current during flash memory erase operations. The system (10a) includes an I/O memory sector (20) divided into (N) subsectors, N being an integer, and a drain pump (40) to generate power for associated erase operations within the N subsectors. An erase sequencing subsystem (60) generates N pulses to enable the erase operations within each of the N subsectors in order to reduce band-to-band tunneling current provided by the drain pump (40).
摘要翻译：提供了一种系统（10a），用于在闪速存储器擦除操作期间减少带内隧穿电流。系统（10a）包括划分为（N）个子部分的N个整数的I / O存储器扇区（20）和用于在N个子部门内产生用于相关联的擦除操作的功率的排水泵（40）。擦除排序子系统（60）产生N个脉冲，以便能够在N个子部门的每一个内进行擦除操作，以便减少由排水泵（40）提供的带间隧穿电流。

3. 发明专利

GB2425201A Memory device and method using positive gate stress to recover overerased cell 未知
公开(公告)号：GB2425201A
公开(公告)日：2006-10-18
申请号：GB0606725
申请日：2004-09-16
申请人： ADVANCED MICRO DEVICES INC
发明人： HAMILTON DARLENE , LIU ZHIZHENG , RANDOLPH MARK W , HE YI , HSIA EDWARD , TANPAIROJ KULACHET , LEE MIMI , MADHANI KLYKHAN
IPC分类号： G11C16/34 , G11C16/04
摘要： A method of erasing a flash electrically erasable read only memory (EEPROM) device composed of a plurality of memory cells (10) includes pre-programming (100) the plurality of memory cells (10), applying an erase pulse (110) to the plurality of memory cells (10) followed by an erase verification (120). The erase verification (120) is followed by soft programming (135) any memory cells having a threshold voltage below a predetermined minimum level (VTMIN) and applying a positive gate stress (130) to the plurality of memory cells (10). The erase method prevents overerasing and provides a tightened threshold voltage distribution.

4. 发明专利

DE60303511T2 未知
公开(公告)号：DE60303511T2
公开(公告)日：2006-09-28
申请号：DE60303511
申请日：2003-04-22
申请人： ADVANCED MICRO DEVICES INC
发明人： LE QUANG , HAMILTON DARLENE , TANPAIROJ KULACHET , LIU ZHIZHENG , HE YI , ZHENG WEI , CHEN PAU-LING , VANBUSKIRK MICHAEL
IPC分类号： G11C16/02 , G11C16/16 , G11C11/56 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： A method of erasing a sector of flash memory cells wherein a first set of preset pre-erase voltages is applied to the sector of flash memory cells. After the first set of preset pre-erase voltages is applied it is determined if another set of preset pre-erase voltages is to be applied to the sector of flash memory cells. If another set of preset pre-erase voltages is applied and if another set of preset pre-erase set of pre-erase voltages is not to be applied, a standard erase routine is applied to the sector.

5. 发明专利

DE60303511D1 未知
公开(公告)号：DE60303511D1
公开(公告)日：2006-04-20
申请号：DE60303511
申请日：2003-04-22
申请人： ADVANCED MICRO DEVICES INC
发明人： LE QUANG , HAMILTON DARLENE , TANPAIROJ KULACHET , LIU ZHIZHENG , HE YI , ZHENG WEI , CHEN PAU-LING , VANBUSKIRK MICHAEL
IPC分类号： G11C16/02 , G11C16/16 , G11C11/56 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： A method of erasing a sector of flash memory cells wherein a first set of preset pre-erase voltages is applied to the sector of flash memory cells. After the first set of preset pre-erase voltages is applied it is determined if another set of preset pre-erase voltages is to be applied to the sector of flash memory cells. If another set of preset pre-erase voltages is applied and if another set of preset pre-erase set of pre-erase voltages is not to be applied, a standard erase routine is applied to the sector.

6. 发明专利

GB2400709B System and method for programming ONO dual bit memory cells 未知
公开(公告)号：GB2400709B
公开(公告)日：2005-12-28
申请号：GB0417770
申请日：2002-12-17
申请人： ADVANCED MICRO DEVICES INC
发明人： HAMILTON DARLENE , THURGATE TIMOTHY , WANG JANET S Y , HAN MICHAEL K , DERHACOBIAN NARBEH
IPC分类号： G11C16/02 , G11C11/56 , G11C16/04 , G11C16/10 , G11C16/34 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： A system and methodology is provided for programming first bit (CO, C2, C4, C6) and second bit (C1, C3, C5, C7) of a memory array (68) of dual bit memory cells (10, 82, 84, 86, 88) at a substantially high delta VT. The substantially higher VT assures that the memory array (68) will maintain programmed data and erase data consistently after higher temperature stresses and/or custumer operation over substantial periods of time. At a substantially higher delta VT, programming of the first bit (C0, C2, C4, C6) of the memory cell (10, 82, 84, 86, 88) causes the second bit (C1, C3, C5, C7) to program harder and faster due to the shorter channel (8) length. Therefore, the present invention employs selected gate and drain voltages and programming pulse widths during programming of the first bit (C0, C2, C4, C6) and second bit (C1, C3, C5, C7) that assures a controlled first bit VT and slows down programming of the second bit (C1,C3, C5, C7). Furthermore, the selected programming parameters keep the programming times short without degrading charge loss.

7. 发明专利

DE10297641T5 未知
公开(公告)号：DE10297641T5
公开(公告)日：2005-01-05
申请号：DE10297641
申请日：2002-12-17
申请人： ADVANCED MICRO DEVICES INC
发明人： HAMILTON DARLENE , THURGATE TIMOTHY , WANG JANET S , HAN MICHAEL K , DERHACOBIAN NARBEH
IPC分类号： G11C16/02 , G11C11/56 , G11C16/04 , G11C16/10 , G11C16/34 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： A system and methodology is provided for programming first bit (CO, C2, C4, C6) and second bit (C1, C3, C5, C7) of a memory array (68) of dual bit memory cells (10, 82, 84, 86, 88) at a substantially high delta VT. The substantially higher VT assures that the memory array (68) will maintain programmed data and erase data consistently after higher temperature stresses and/or custumer operation over substantial periods of time. At a substantially higher delta VT, programming of the first bit (C0, C2, C4, C6) of the memory cell (10, 82, 84, 86, 88) causes the second bit (C1, C3, C5, C7) to program harder and faster due to the shorter channel (8) length. Therefore, the present invention employs selected gate and drain voltages and programming pulse widths during programming of the first bit (C0, C2, C4, C6) and second bit (C1, C3, C5, C7) that assures a controlled first bit VT and slows down programming of the second bit (C1,C3, C5, C7). Furthermore, the selected programming parameters keep the programming times short without degrading charge loss.

8. 发明专利

AU2002367512A1 System and method for programming ono dual bit memory cells 未知
公开(公告)号：AU2002367512A1
公开(公告)日：2003-09-02
申请号：AU2002367512
申请日：2002-12-17
申请人： ADVANCED MICRO DEVICES INC
发明人： THURGATE TIMOTHY , WANG JANET S Y , DERHACOBIAN NARBEH , HAMILTON DARLENE , HAN MICHAEL K
IPC分类号： G11C16/02 , G11C11/56 , G11C16/04 , G11C16/10 , G11C16/34 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： A system and methodology is provided for programming first bit (CO, C2, C4, C6) and second bit (C1, C3, C5, C7) of a memory array (68) of dual bit memory cells (10, 82, 84, 86, 88) at a substantially high delta VT. The substantially higher VT assures that the memory array (68) will maintain programmed data and erase data consistently after higher temperature stresses and/or custumer operation over substantial periods of time. At a substantially higher delta VT, programming of the first bit (C0, C2, C4, C6) of the memory cell (10, 82, 84, 86, 88) causes the second bit (C1, C3, C5, C7) to program harder and faster due to the shorter channel (8) length. Therefore, the present invention employs selected gate and drain voltages and programming pulse widths during programming of the first bit (C0, C2, C4, C6) and second bit (C1, C3, C5, C7) that assures a controlled first bit VT and slows down programming of the second bit (C1,C3, C5, C7). Furthermore, the selected programming parameters keep the programming times short without degrading charge loss.

9. 发明专利

GB2427771B Method of dual cell memory device operation for improved end-of-life read margin 未知
公开(公告)号：GB2427771B
公开(公告)日：2007-04-25
申请号：GB0615514
申请日：2004-03-08
申请人： ADVANCED MICRO DEVICES INC
发明人： HAMILTON DARLENE , TANPAIROJ KULACHET , HSIA EDWARD , LEE MIMI , MADHANI ALYKHAN
IPC分类号： G11C16/34 , G11C20060101 , G11C11/34 , G11C11/56 , G11C16/04 , G11C16/10
摘要： A method of programming a dual cell memory device having a first charge storing cell and a second charge storing cell. According to one aspect of the method, the method can include over-erasing the first and second charge storing cells to shift an erase state threshold voltage of the memory device to be lower than a natural state threshold voltage. According to another aspect of the method, the method can include programming the first and second charge storing cells to the same data state and verifying that the second programmed charge storing cell stores charge corresponding to the data state. If the verification fails, both charge storing cells can be re-pulsed.

10. 发明专利

GB2415552B Method of dual cell memory device operation for improved end-of-life read margin 未知
公开(公告)号：GB2415552B
公开(公告)日：2006-12-27
申请号：GB0518482
申请日：2004-03-08
申请人： ADVANCED MICRO DEVICES INC
发明人： HAMILTON DARLENE , TANPAIROJ KULACHET , HSIA EDWARD , MADHANI ALYKHAN , LEE MIMI
IPC分类号： G11C16/10 , G11C20060101 , G11C11/34 , G11C11/56 , G11C16/04 , G11C16/34
摘要： A method of programming a dual cell memory device having a first charge storing cell and a second charge storing cell. According to one aspect of the method, the method can include over-erasing the first and second charge storing cells to shift an erase state threshold voltage of the memory device to be lower than a natural state threshold voltage. According to another aspect of the method, the method can include programming the first and second charge storing cells to the same data state and verifying that the second programmed charge storing cell stores charge corresponding to the data state. If the verification fails, both charge storing cells can be re-pulsed.

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