专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO02080181A3 I/O PARTITIONING SYSTEM AND METHODOLOGY TO REDUCE BAND-TO-BAND TUNNELING CURRENT DURING ERASE 审中-公开
标题翻译： I / O分区系统和方法，以减少擦除期间的带对带隧道电流
公开(公告)号：WO02080181A3
公开(公告)日：2003-01-09
申请号：PCT/US0143543
申请日：2001-11-14
申请人： ADVANCED MICRO DEVICES INC , FUJITSU LTD
发明人： BAUTISTA EDWARD V JR , KURIHARA KAZUHIRO , PAN FENG , LEE WENG FOOK , SUNKAVALLI RAVI , HAMILTON DARLENE
IPC分类号： G11C16/02 , G11C16/06 , G11C16/16 , G11C16/34 , G11C16/30
CPC分类号： G11C16/3445 , G11C16/16 , G11C16/344
摘要： A system (10a) is provided for reducing band-to-band tunneling current during flash memory erase operations. The system (10a) includes an I/O memory sector (20) divided into (N) subsectors, N being an integer, and a drain pump (40) to generate power for associated erase operations within the N subsectors. An erase sequencing subsystem (60) generates N pulses to enable the erase operations within each of the N subsectors in order to reduce band-to-band tunneling current provided by the drain pump (40).
摘要翻译：提供了一种系统（10a），用于在闪速存储器擦除操作期间减少带内隧穿电流。系统（10a）包括划分为（N）个子部分的N个整数的I / O存储器扇区（20）和用于在N个子部门内产生用于相关联的擦除操作的功率的排水泵（40）。擦除排序子系统（60）产生N个脉冲，以便能够在N个子部门的每一个内进行擦除操作，以便减少由排水泵（40）提供的带间隧穿电流。

2. 发明申请

WO02082447A3 SOFT PROGRAM AND SOFT PROGRAM VERIFY OF THE CORE CELLS IN FLASH MEMORY ARRAY 审中-公开
标题翻译：闪存存储阵列中核心单元的软件程序和软件程序验证
公开(公告)号：WO02082447A3
公开(公告)日：2003-03-06
申请号：PCT/US0148734
申请日：2001-12-12
申请人： ADVANCED MICRO DEVICES INC , FUJITSU LTD
发明人： YACHARENI SANTOSH K , HAMILTON DARLENE G , LE BINH Q , KURIHARA KAZUHIRO
IPC分类号： G11C16/02 , G11C16/06 , G11C16/34
CPC分类号： G11C16/3409 , G11C16/0475 , G11C16/3404 , G11C16/3436
摘要： A method (900) and system (400) are disclosed for memory cell soft program and soft program verify, to adjust, or correct the threshold voltage (350) between a target minimum (380) and maximum (390), which may be employed in assoication with a dual bit memory cell architecture (50). The method (900) includes applying one reference voltage signal (455) to the over erased core cell, and a diference cell (480), comparing the two currents (475) produced by each, selectively verifying (485, 435) proper soft programming of one or more bits of the cell (405), determining that the dual bit memory cell is properly soft programmed (950). The method may also comprise selectively re-verifying (950, 955) proper soft programming of the cells after selectively soft programming (965) at least one or more bits (980) of the cell.
摘要翻译：公开了用于存储器单元软程序和软程序验证的方法（900）和系统（400），以调整或校正目标最小值（380）和最大值（390）之间的阈值电压（350），其可以被采用与双位存储器单元架构（50）相关联。方法（900）包括将一个参考电压信号（455）应用于过擦除的核心单元和不同单元（480），比较由每一个选择性验证（485,435）适当的软编程产生的两个电流（475）（405）的一个或多个比特，确定双位存储器单元被适当地软编程（950）。该方法还可以包括在对该小区的至少一个或多个比特（980）进行选择性软编程（965）之后，选择性地重新验证（950,995）小区的适当的软编程。

3. 发明申请

WO0197230A3 METHOD TO REDUCE CAPACITIVE LOADING IN FLASH MEMORY X-DECODER FOR ACCURATE VOLTAGE CONTROL AT WORDLINES AND SELECT LINES 审中-公开
标题翻译：降低闪存存储器X-DECODER中电容负载的方法，用于在WORDLINES和SELECT LINE中进行精确的电压控制
公开(公告)号：WO0197230A3
公开(公告)日：2002-05-30
申请号：PCT/US0118081
申请日：2001-06-04
申请人： ADVANCED MICRO DEVICES INC , FUJITSU LTD
发明人： LE BINH Q , KURIHARA KAZUHIRO , CHEN PAU-LING
IPC分类号： G11C16/06 , G11C16/02 , G11C16/04 , G11C16/08 , G11C16/30 , G11C5/14
CPC分类号： G11C16/08
摘要： An apparatus and a method for reducing capacitive loading in a Flash memory X-decoder so as to accurately control the voltages at selected wordlines and block select lines are provided. A decoding structure (18) separately applies a first boosted voltages to the wordline N-well region and a second boosted voltage to the selected wordline so as to reduce capacitive loading on the selected wordline due to heavy capacitive loading associated with the wordline N-well region. The decoding structure further applies a third boosted voltage to the select gate N-well region and a fourth boosted voltage to the block select line so as to reduce capacitive loading on the block select line due to heavy capacitive loading associated with the select gate N-well region. As a consequence, an accurate voltage can be created quickly at the selected wordline since its capacitive loading path is very small.
摘要翻译：提供了一种用于降低闪存X解码器中的电容负载以便精确地控制所选字线和块选择线上的电压的装置和方法。解码结构（18）分别将第一升压电压施加到字线N阱区域并将第二升压电压施加到所选择的字线，以便由于与字线N阱相关联的重电容性负载而减小所选字线上的容性负载地区。解码结构还将第三升压电压施加到选择栅极N阱区域，并将第四升压电压施加到块选择线，以便由于与选择栅极N相关联的重电容负载而减小块选择线上的电容负载，井区。因此，由于其电容加载路径非常小，所以可以在所选字线处快速创建精确的电压。

4. 发明专利

AU2002230944A1 Soft program and soft program verify of the core cells in flash memory array 未知
公开(公告)号：AU2002230944A1
公开(公告)日：2002-10-21
申请号：AU2002230944
申请日：2001-12-12
申请人： FUJITSU LTD , ADVANCED MICRO DEVICES INC
发明人： YACHARENI SANTOSH K , LE BINH Q , HAMILTON DARLENE G , KURIHARA KAZUHIRO
IPC分类号： G11C16/02 , G11C16/06 , G11C16/34
摘要： A method and system are disclosed for memory cell soft program and soft program verify, to adjust, or correct the threshold voltage between a target minimum and maximum, which may be employed in association with a dual bit memory cell architecture. The method includes applying one reference voltage signal to the over erased core cell, and a different reference voltage signal to the reference cell, comparing the two currents produced by each, selectively verifying proper soft programming of one or more bits of the cell, determining that the dual bit memory cell is properly soft programmed. The method may also comprise selectively re-verifying proper soft programming of the cells after selectively soft programming at least one or more bits of the cell.

5. 发明专利

AU6670101A Method to reduce capacitive loading in flash memory x-decoder for accurate voltage control at wordlines and select lines 未知
公开(公告)号：AU6670101A
公开(公告)日：2001-12-24
申请号：AU6670101
申请日：2001-06-04
申请人： ADVANCED MICRO DEVICES INC , FUJITSU LTD
发明人： LE BINH Q , KURIHARA KAZUHIRO , CHEN PAU-LING
IPC分类号： G11C16/06 , G11C16/02 , G11C16/04 , G11C16/08
摘要： An apparatus and a method for reducing capacitive loading in a Flash memory X-decoder so as to accurately control the voltages as selected wordlines and block select lines are provided. A decoding structure separately applies a first boosted voltage to the wordline N-well region and a second boosted voltage to the selected wordline so as to reduce capacitive loading on the selected wordline due to heavy capacitive loading associated with the wordline N-well region. The decoding structure further applies a third boosted voltage to the select gate N-well region and a fourth boosted voltage to the block select line so as to reduce capacitive loading on the block select line due to heavy capacitive loading associated with the select gate N-well region. As a consequence, an accurate voltage can be created quickly at the selected wordline since its capacitive loading path is very small.

6. 发明专利

GB2391985B I/O partitioning system and methodology to reduce band-to-band tunneling current during erase 未知
公开(公告)号：GB2391985B
公开(公告)日：2004-11-24
申请号：GB0324642
申请日：2001-11-14
申请人： ADVANCED MICRO DEVICES INC , FUJITSU LTD , AMD , AMD INVESTMENTS INC , FASL LLC , SPANSION LLC
发明人： BAUTISTA JR EDWARD V , KURIHARA KAZUHIRO , LEE WENG FOOK , PAN FENG , SUNKAVALLI RAVI , HAMILTON DARLENE
IPC分类号： G11C16/02 , G11C16/06 , G11C16/16 , G11C16/34
摘要： A system is provided for reducing band-to-band tunneling current during Flash memory erase operations. The system includes a memory sector divided into (N) I/O subsectors, N being an integer, and a drain pump to generate power for associated erase operations within the N I/O subsectors. An erase sequencing subsystem generates N pulses to enable the erase operations within each of the N I/O subsectors in order to reduce band-to-band tunneling current provided by the drain pump.

7. 发明专利

AU2003245450A8 Column-decoding and precharging in a flash memory device 未知
公开(公告)号：AU2003245450A8
公开(公告)日：2004-03-11
申请号：AU2003245450
申请日：2003-06-10
申请人： ADVANCED MICRO DEVICES INC , FUJITSU LTD , FASL LLC
发明人： KURIHARA KAZUHIRO , CHEN PAU-LING , WONG KEITH , CHUNG MICHAEL S , YANG TIEN-CHUNG , SHIEH MING-HUEI
IPC分类号： G11C16/06 , G11C16/04 , G11C16/26

8. 发明专利

GB2391985A I/O partitioning system and methodology to reduce band-to-band tunneling current during erase 未知
公开(公告)号：GB2391985A
公开(公告)日：2004-02-18
申请号：GB0324642
申请日：2001-11-14
申请人： ADVANCED MICRO DEVICES INC , FUJITSU LTD
发明人： BAUTISTA JR EDWARD V , KURIHARA KAZUHIRO , LEE WENG FOOK , PAN FENG , SUNKAVALLI RAVI , HAMILTON DARLENE
IPC分类号： G11C16/02 , G11C16/06 , G11C16/16 , G11C16/34
摘要： A system (10a) is provided for reducing band-to-band tunneling current during flash memory erase operations. The system (10) includes an I/O memory sector (20) divided into (N) subsectors, N being an integer, and a drain pump (40) to generate power for associated erase operations within the N subsectors. An erase sequencing subsystem (60) generates N pulses to enable the erase operations within each of the N subsectors in order to reduce band-to-band tunneling current provided by the drain pump (40).

9. 发明专利

AU2002239301A1 I/o partitioning system and methodology to reduce band-to-band tunneling current during erase 未知
公开(公告)号：AU2002239301A1
公开(公告)日：2002-10-15
申请号：AU2002239301
申请日：2001-11-14
申请人： ADVANCED MICRO DEVICES INC , FUJITSU LTD
发明人： KURIHARA KAZUHIRO , LEE WENG FOOK , SUNKAVALLI RAVI , BAUTISTA EDWARD V JR , PAN FENG , HAMILTON DARLENE
IPC分类号： G11C16/02 , G11C16/06 , G11C16/16 , G11C16/34 , G11C16/30
摘要： A system is provided for reducing band-to-band tunneling current during Flash memory erase operations. The system includes a memory sector divided into (N) I/O subsectors, N being an integer, and a drain pump to generate power for associated erase operations within the N I/O subsectors. An erase sequencing subsystem generates N pulses to enable the erase operations within each of the N I/O subsectors in order to reduce band-to-band tunneling current provided by the drain pump.

10. 发明专利

DE60011921T2 未知
公开(公告)号：DE60011921T2
公开(公告)日：2005-07-14
申请号：DE60011921
申请日：2000-10-07
申请人： ADVANCED MICRO DEVICES INC , FUJITSU LTD
发明人： AKAOGI TAKAO , CHEN TIEN-MIN , KURIHARA KAZUHIRO
IPC分类号： G11C16/06 , G11C16/02 , G11C16/26
摘要： A pre-amplifier portion of a sense amplifier for a dual bank architecture simultaneous operation flash memory device is provided. The sense pre-amplifier circuit includes two inverting amplifiers, the second inverting amplifier providing a feedback loop for the first inverting amplifier. In addition, special "kicker" circuitry raises the sense pre-amplifier's input signal line to its operating level. The combination of inverting amplifiers, feedback loop and level raising circuitry is configured to provide higher bandwidths for the sense pre-amplifier to accommodate low capacitive loading resulting from a small memory bank. The combination is also configured to provide faster raising of the input signal line to operating level to accommodate high capacitive loading resulting from a large memory bank. The combination is also configured to provide increased signal margins at the output of the sense pre-amplifier.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式