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1. 发明公开

KR1020080043097A 표시 장치 无效
标题翻译：显示设备
公开(公告)号：KR1020080043097A
公开(公告)日：2008-05-16
申请号：KR1020060111707
申请日：2006-11-13
申请人： 삼성전자주식회사
发明人： 이영욱 , 이우근 , 전경숙 , 차연희 , 김종인
IPC分类号： G02F1/133 , G09G3/36 , G09G3/20 , G02F1/1343
CPC分类号： G02F1/136286 , G02F1/13306 , H01L27/124 , H01L29/41733
摘要： A display device is provided to restrain kickback effect even if a mask is misaligned and to thereby improve the display quality. A display device includes a plurality of gate lines(22), a plurality of data lines(42), a plurality of thin film transistors, a plurality of pixel electrodes(72), a plurality of dummy gate lines(26), and a compensation capacitor. The gate lines receive gate on/off voltage. The data lines are insulated from the gate lines. Each of the thin film transistors includes a gate electrode(24) connected to a corresponding gate line, a drain electrode(45) connected to a corresponding data line, and a source electrode(62) formed apart from the drain electrode. The pixel electrodes are connected to the source electrodes, respectively. The dummy gate lines receive kickback compensation voltage having a phase opposite to the gate on/off voltage. The compensation capacitor includes a dummy gate electrode connected to a dummy gate lines and a dummy source electrode(64) insulated from the dummy gate electrode and connected to a corresponding pixel electrode.
摘要翻译：提供一种显示装置，以便即使掩模未对准来抑制反冲效果，从而提高显示质量。显示装置包括多个栅极线（22），多个数据线（42），多个薄膜晶体管，多个像素电极（72），多个虚拟栅极线（26）和补偿电容器。栅极线接收栅极导通/截止电压。数据线与栅极线绝缘。每个薄膜晶体管包括连接到对应的栅极线的栅电极（24），连接到对应数据线的漏电极（45）和与漏电极分开形成的源电极（62）。像素电极分别连接到源电极。虚拟栅极线接收具有与栅极导通/截止电压相反的相位的反冲补偿电压。补偿电容器包括连接到虚拟栅极线的伪栅电极和与虚拟栅电极绝缘并连接到相应的像素电极的虚拟源电极（64）。

2. 发明公开

KR1020080030877A 액정표시장치 无效
标题翻译：液晶显示装置
公开(公告)号：KR1020080030877A
公开(公告)日：2008-04-07
申请号：KR1020060097421
申请日：2006-10-02
申请人： 삼성전자주식회사
发明人： 이영욱 , 이우근 , 조의식 , 차연희
IPC分类号： G02F1/1343
CPC分类号： G02F1/1362 , G02F1/136286 , G02F1/1368 , G02F2001/136218 , G02F2001/13629
摘要： An LCD(Liquid Crystal Display) is provided to form a shield electrode and apply a higher voltage than a common voltage to the shield electrode, thereby reducing image sticking. An LCD includes a first substrate(111), a second substrate(211) and a liquid crystal layer(300). The second substrate includes a common electrode(251) to which a common voltage is applied. The liquid crystal layer is interposed between the first and second substrates. The first substrate includes a data line(141), an insulating layer(151) formed on the data line and a shield electrode(165) formed on the insulating layer along the data line. A voltage higher than the common voltage is applied to the shield electrode.
摘要翻译：提供LCD（液晶显示器）以形成屏蔽电极，并向屏蔽电极施加比公共电压更高的电压，从而减少图像残留。 LCD包括第一基板（111），第二基板（211）和液晶层（300）。第二基板包括施加公共电压的公共电极（251）。液晶层介于第一和第二基板之间。第一基板包括数据线（141），形成在数据线上的绝缘层（151）和沿数据线形成在绝缘层上的屏蔽电极（165）。将高于公共电压的电压施加到屏蔽电极。

3. 发明公开

KR1020080004005A 박막 트랜지스터 기판의 제조 방법 无效
标题翻译：薄膜晶体管基板制造方法
公开(公告)号：KR1020080004005A
公开(公告)日：2008-01-09
申请号：KR1020060062424
申请日：2006-07-04
申请人： 삼성전자주식회사
发明人： 이영욱 , 이우근 , 오화열 , 차연희 , 박정인
IPC分类号： G02F1/136
CPC分类号： G02F1/136 , G03F1/144 , H01L27/124 , H01L29/786 , H01L51/56
摘要： A method of fabricating a thin film transistor substrate is provided to reduce a channel length between a source electrode and a drain electrode of a thin film transistor through a single slit mask having a notch. A gate pattern including a gate line and a gate electrode(20) is formed. A gate insulating layer(30), an active layer(40), an ohmic-contact layer(45) and a data metal layer are formed on the gate pattern. A channel of a thin film transistor and a data pattern including a source electrode(60), a drain electrode(70) and a data line(50) are formed at the data metal layer by using a single slit mask including a notch. A passivation layer and a pixel electrode(100) connected with the drain electrode are formed on the data pattern. The forming of the channel of the thin film transistor and the data pattern includes forming photoresist on the data metal layer, exposing the photoresist by using the single slit mask, and etching the data metal layer without a patterned photoresist pattern.
摘要翻译：提供一种制造薄膜晶体管衬底的方法，通过具有缺口的单个狭缝掩模来减小薄膜晶体管的源电极和漏电极之间的沟道长度。形成包括栅极线和栅电极（20）的栅极图案。在栅极图案上形成栅绝缘层（30），有源层（40），欧姆接触层（45）和数据金属层。通过使用包括凹口的单个狭缝掩模，在数据金属层上形成薄膜晶体管的沟道和包括源极（60），漏极（70）和数据线（50）的数据图案。在数据图形上形成钝化层和与漏电极连接的像素电极（100）。薄膜晶体管的通道的形成和数据图形包括在数据金属层上形成光致抗蚀剂，通过使用单个狭缝掩模曝光光致抗蚀剂，并且在没有图案化的光致抗蚀剂图案的情况下蚀刻数据金属层。

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