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1. 发明授权

KR102025597B1 반도체 소자 有权
公开(公告)号：KR102025597B1
公开(公告)日：2019-09-26
申请号：KR1020130007222
申请日：2013-01-23
申请人： 삼성전자주식회사
发明人： 송현승 , 김경은 , 박재균
IPC分类号： H01L27/02

2. 发明公开

KR1020010036770A 반도체 장치의 마스크 제조 방법 无效
标题翻译：半导体器件制造方法
公开(公告)号：KR1020010036770A
公开(公告)日：2001-05-07
申请号：KR1019990043898
申请日：1999-10-11
申请人： 삼성전자주식회사
发明人： 이대엽 , 박재균
IPC分类号： H01L21/027
摘要： PURPOSE: A method for manufacturing a mask of a semiconductor device is provided to improve the resolution when performing a photo-etching process. CONSTITUTION: The first photoresist layer is formed on an upper portion of a material layer(100) as a patterning object. The first photoresist layer is exposed by the first light source. A water-soluble material layer(102) is formed on an upper portion of the first photoresist layer. The water-soluble material layer(102) is not reacted with the first photoresist layer. The second photoresist layer is formed on the water-soluble material layer(102). The second photoresist layer is exposed by the second light source.
摘要翻译：目的：提供一种制造半导体器件的掩模的方法，以在进行光蚀刻工艺时提高分辨率。构成：第一光致抗蚀剂层形成在作为图案形成对象的材料层（100）的上部。第一光致抗蚀剂层被第一光源曝光。在第一光致抗蚀剂层的上部形成水溶性材料层（102）。水溶性材料层（102）不与第一光致抗蚀剂层反应。第二光致抗蚀剂层形成在水溶性材料层（102）上。第二光致抗蚀剂层被第二光源曝光。

3. 发明授权

KR101561061B1 돌출형 소자 분리막을 가지는 반도체 소자 有权
标题翻译：具有突起型隔离层的半导体器件
公开(公告)号：KR101561061B1
公开(公告)日：2015-10-16
申请号：KR1020090031427
申请日：2009-04-10
申请人： 삼성전자주식회사
发明人： 김동현 , 박재균
IPC分类号： H01L21/762 , H01L21/28
CPC分类号： H01L21/76897 , H01L21/0217 , H01L21/308 , H01L21/76224 , H01L27/0207 , H01L27/10876 , H01L27/10885 , H01L27/10888 , H01L29/66621 , Y10S257/906 , Y10S257/907
摘要： 본발명은돌출형소자분리막을가지는반도체소자를제공한다. 본발명에따른돌출형소자분리막을포함하는반도체소자는, 볼록부, 상기볼록부를둘러싸는오목부, 상기볼록부를가로지르고라인형상을가지는하나또는그 이상의트랜치들을포함하는반도체층; 상기오목부를충진하고, 상기볼록부의최상측표면에비하여높은수준을가지도록연장된소자분리막; 상기하나또는그 이상의트랜치내에형성된하나또는그 이상의게이트구조물들; 및상기볼록부의일부상에전기적으로연결되도록형성되고, 상기소자분리막에의하여둘러싸인콘택플러그;를포함한다.
摘要翻译：半导体器件可以包括具有凸部的半导体层和围绕凸部的凹部。半导体器件还可以包括填充凹部并向上延伸的突起型隔离层，使得隔离层的最上表面比凸部的最上表面高一级。

4. 发明授权

KR100456688B1 완전 씨모스 에스램 셀 有权
标题翻译： 완전씨모스에스램셀
公开(公告)号：KR100456688B1
公开(公告)日：2004-11-10
申请号：KR1020020000677
申请日：2002-01-07
申请人： 삼성전자주식회사
发明人： 김성봉 , 정순문 , 박재균
IPC分类号： H01L27/11 , H01L21/8244
CPC分类号： H01L27/11 , H01L27/1104
摘要： SRAM cells and devices are provided. The SRAM cells may share connections with neighboring cells, including ground, power supply voltage and/or bit line connections. SRAM cells and devices are also provided that include first and second active regions disposed at a semiconductor substrate. Parallel first and second gate electrodes cross over the first and second active regions. One end of the first active region adjacent to the first gate electrode is electrically connected to the second active region adjacent to the first gate electrode through a first node line parallel to the first gate electrode, and the other end of the first active region adjacent to the second gate electrode is electrically connected to the second active region adjacent to the second gate electrode through a second node line parallel to the second gate electrode. The first node line is electrically connected to the second gate electrode through a first local interconnection crossing over the first node line, and the second node line is electrically connected to the first gate electrode through a second local interconnection crossing over the second node line. Additionally, a word line may be in direct contact with gate electrodes of transfer transistors of the SRAM cells.
摘要翻译：提供SRAM单元和器件。 SRAM单元可以共享与相邻单元的连接，包括接地，电源电压和/或位线连接。还提供了SRAM单元和器件，其包括设置在半导体衬底处的第一和第二有源区。平行的第一和第二栅电极跨过第一和第二有源区。与第一栅电极相邻的第一有源区的一端通过平行于第一栅电极的第一节点线电连接到与第一栅电极相邻的第二有源区，并且第一有源区的另一端与第二栅电极通过平行于第二栅电极的第二节点线电连接到与第二栅电极相邻的第二有源区。第一节点线通过在第一节点线上交叉的第一局部互连而电连接到第二栅电极，并且第二节点线通过在第二节点线上交叉的第二局部互连电连接到第一栅电极。另外，字线可以与SRAM单元的传输晶体管的栅极直接接触。

5. 发明公开

KR1020030060142A 완전 씨모스 에스램 셀 有权
标题翻译：全CMOS SRAM单元
公开(公告)号：KR1020030060142A
公开(公告)日：2003-07-16
申请号：KR1020020000677
申请日：2002-01-07
申请人： 삼성전자주식회사
发明人： 김성봉 , 정순문 , 박재균
IPC分类号： H01L27/11 , H01L21/8244
CPC分类号： H01L27/11 , H01L27/1104
摘要： PURPOSE: A full CMOS(Complementary Metal Oxide Semiconductor) SRAM(Static Random Access Memory) cell is provided to be capable of being operated at a low supply voltage and improving the degree of integration. CONSTITUTION: A full CMOS SRAM cell is provided with the first and second active region, the first gate electrode(39A) located across the upper portion of the first and second active region, the second gate electrode(39B) located parallel with the first gate electrode, the first node line(58N') located parallel with the first gate electrode for electrically connecting between one end of the first active region near the first gate electrode and the second active region near the first gate electrode, the second node line(58N'') located parallel with the second gate electrode for electrically connecting between the other end of the first active region near the second gate electrode and the second active region near the second gate electrode, the first local line(731') located across the upper portion of the first node line and the second gate electrode, and the second local line(731'') located across the upper portion of the second node line and the first gate electrode.
摘要翻译：目的：提供完整的CMOS（互补金属氧化物半导体）SRAM（静态随机存取存储器）单元，能够在低电源电压下工作并提高集成度。构成：全CMOS SRAM单元设置有第一和第二有源区，第一栅电极（39A）位于第一和第二有源区的上部，第二栅电极（39B）与第一栅极平行所述第一节点线（58N'）与所述第一栅电极平行，用于电连接所述第一栅电极附近的所述第一有源区的一端与所述第一栅极附近的所述第二有源区，所述第二节点线（58N “），其与第二栅电极平行，用于电连接在第二栅电极附近的第一有源区的另一端和靠近第二栅电极的第二有源区之间，第一局部线（731'）跨越上第一节点线和第二栅电极的部分，以及跨越第二节点线的上部和第一栅电极的第二局部线（731“）。

6. 发明公开

KR1019970077282A 반도체 기판 세정 용액 失效
标题翻译：半导体基板清洗液
公开(公告)号：KR1019970077282A
公开(公告)日：1997-12-12
申请号：KR1019960018521
申请日：1996-05-29
申请人： 삼성전자주식회사
发明人： 박재균 , 최영준
IPC分类号： H01L21/304
摘要： 본 발명은 반도체 기판 세정 용액에 관한 것이다. 하기 식(Ⅰ)로 표시되는 불화암모늄, 불산 및 탈이온수를 포함하는 세정 용액을 이용하면, 현상 공정 후에 표면에 남아 있는 유기 물질을 효과적으로 제거할 수 있다.
RNH
3 F ( I )
여기에서, R은 C
2 ∼C
18 탄화수소임.

7. 发明公开

KR1020140094782A 반도체 소자 审中-实审
标题翻译：半导体器件
公开(公告)号：KR1020140094782A
公开(公告)日：2014-07-31
申请号：KR1020130007222
申请日：2013-01-23
申请人： 삼성전자주식회사
发明人： 송현승 , 김경은 , 박재균
IPC分类号： H01L27/02
CPC分类号： H01L27/0207 , H01L27/1104 , H01L2027/11812 , H01L2027/11838
摘要： A semiconductor device according to the present invention prepares a substrate including first and second active areas, which are adjacent to each other, and an element separation area between the first and second active areas. A first gate pattern and a second gate pattern which is arranged in parallel with the first pattern in a first direction are placed on the first active area. A third gate pattern which is formed into the asymmetric shape with the first gate pattern according to the first direction is placed on the second active area. Also, a fourth gate pattern, which is arranged in parallel with the third gate pattern in the first direction and is formed in the asymmetric shape with the second gate pattern based on the first direction, is placed on the second active area. The semiconductor device can be integrated with high density because the gate patterns are formed in the asymmetric shape.
摘要翻译：根据本发明的半导体器件准备包括彼此相邻的第一和第二有源区以及第一和第二有源区之间的元件分离区的衬底。在第一有效区域上放置有与第一图案平行地沿第一方向布置的第一栅极图案和第二栅极图案。根据第一方向形成具有第一栅极图案的不对称形状的第三栅极图案被放置在第二有源区域上。而且，第四栅极图案被放置在第二有源区域上，第四栅极图案在第一方向上与第三栅极图案平行布置并且以不对称形状形成第二栅极图案。半导体器件可以以高密度积分，因为栅极图案形成为不对称形状。

8. 发明公开

KR1020010001155A 얼라인먼트 정밀도의 개선 방법 无效
标题翻译：改善对准精度的方法
公开(公告)号：KR1020010001155A
公开(公告)日：2001-01-05
申请号：KR1019990020197
申请日：1999-06-02
申请人： 삼성전자주식회사
发明人： 진수복 , 박재균
IPC分类号： H01L21/027
摘要： PURPOSE: A method for improving alignment precision is provided to perform an alignment regarding a plurality of different preceding layers in an exposure apparatus without an additional photo process regarding a sample wafer. CONSTITUTION: Respective coordinate values of alignment marks generated in a plurality of different preceding layers are measured during an exposure process in an exposure apparatus. Alignment correction values are calculated by converting the respective measurement values of the alignment marks, and an alignment process is performed regarding the plurality of different preceding layers.
摘要翻译：目的：提供一种用于提高对准精度的方法，以在曝光装置中执行关于多个不同的先前层的对准，而不需要关于样品晶片的附加照相处理。构成：在曝光装置中的曝光处理期间测量在多个不同的先前层中产生的对准标记的相应坐标值。通过转换对准标记的各个测量值来计算对准校正值，并且对多个不同的先前层进行对准处理。

9. 发明公开

KR1020000002251A 산화막 소모를 저감하기 위한 반도체 소자 제조방법 无效
标题翻译：用于消耗氧化膜消耗的半导体器件的制造方法
公开(公告)号：KR1020000002251A
公开(公告)日：2000-01-15
申请号：KR1019980022912
申请日：1998-06-18
申请人： 삼성전자주식회사
发明人： 박재균 , 한영국
IPC分类号： H01L21/328
摘要： PURPOSE: A manufacturing method for a semiconductor device is provided to lessen a consumption of an oxide film for minimizing a base leaking current of a transistor. CONSTITUTION: A manufacturing method for a semiconductor element comprises: operating a plastic flow to a photo-resist film formed by a base photo process for lessening an etching damage of a device separating oxide film; and etching deposited films for exposing one part of a silicon substrate for base ion injection after a base photo process in a bipolar for a static random access memory(SRAM).
摘要翻译：目的：提供一种用于半导体器件的制造方法，以减少用于使晶体管的基极泄漏电流最小化的氧化膜的消耗。构成：半导体元件的制造方法包括：对通过基底光刻工艺形成的光致抗蚀剂膜进行塑性流动，以减少隔离氧化膜的器件的蚀刻损伤; 并且在用于静态随机存取存储器（SRAM）的双极性的基础照相处理之后，蚀刻用于暴露一部分用于基底离子注入的硅衬底的沉积膜。

10. 发明公开

KR1020100112901A 돌출형 소자 분리막을 가지는 반도체 소자 有权
标题翻译：具有推荐型隔离层的半导体器件
公开(公告)号：KR1020100112901A
公开(公告)日：2010-10-20
申请号：KR1020090031427
申请日：2009-04-10
申请人： 삼성전자주식회사
发明人： 김동현 , 박재균
IPC分类号： H01L21/762 , H01L21/28
CPC分类号： H01L21/76897 , H01L21/0217 , H01L21/308 , H01L21/76224 , H01L27/0207 , H01L27/10876 , H01L27/10885 , H01L27/10888 , H01L29/66621 , Y10S257/906 , Y10S257/907
摘要： PURPOSE: A semiconductor device including a protruded device isolation layer is provided to increase a contact region by providing a protruded device isolation layer which is higher than a gate structure. CONSTITUTION: A device isolation layer(110) is formed on part of a semiconductor layer(100). The device isolation layer is protruded from a semiconductor layer. A device isolation layer includes a plurality of openings(108) to partially expose the semiconductor layer. The semiconductor layer exposed by the plurality of openings is an active region(120). A gate structure is formed in the active region.
摘要翻译：目的：提供包括突出器件隔离层的半导体器件，通过提供高于栅极结构的突出器件隔离层来增加接触区域。构成：在半导体层（100）的一部分上形成器件隔离层（110）。器件隔离层从半导体层突出。器件隔离层包括多个部分地暴露半导体层的开口（108）。由多个开口暴露的半导体层是有源区（120）。在有源区中形成栅极结构。

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