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1. 发明专利

JP5155843B2 Information processing apparatus and a neural network circuit using the same 有权
公开(公告)号：JP5155843B2
公开(公告)日：2013-03-06
申请号：JP2008326313
申请日：2008-12-22
申请人：シャープ株式会社 , 隆森江
发明人：茂夫大西 , 隆森江
IPC分类号： G06G7/60 , G06N3/063
CPC分类号： G11C11/54 , G06N3/063 , G11C13/0002

3. 发明专利

JPWO2007026509A1 可変抵抗素子及びその製造方法审中-公开
公开(公告)号：JPWO2007026509A1
公开(公告)日：2009-03-05
申请号：JP2007533149
申请日：2006-08-08
申请人：シャープ株式会社 , 独立行政法人産業技術総合研究所
发明人：康成細井 , 康成細井 , 茂夫大西 , 茂夫大西 , 荻本　泰史 , 泰史荻本 , 岡　隆史 , 隆史岡 , 直人永長 , 直人永長 , 十倉　好紀 , 好紀十倉
IPC分类号： H01L49/00 , H01L27/10 , H01L45/00
CPC分类号： H01C7/1013 , G11C13/0007 , G11C2213/15 , G11C2213/31 , H01C7/115 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/147
摘要： 2つの金属電極の間に強相関材料からなる可変抵抗体を設けてなり、金属電極間に電圧パルスを印加することにより金属電極間の電気抵抗が変化する可変抵抗素子において、明確なスイッチング動作原理の裏付けによって、金属電極及び可変抵抗体を適切に設計して、電気抵抗の低抵抗状態と高抵抗状態間の抵抗比の大きなスイッチング動作を可能とする可変抵抗素子を提供する。電圧パルスの印加によって、2つの金属電極1,3の何れか一方の第1電極と可変抵抗体2の界面において金属絶縁体転移が生じるように第1電極と可変抵抗体の材料及び組成を設定する。更に、第1電極と可変抵抗体の仕事関数差が、可変抵抗体の第1電極との界面近傍において金属相と絶縁体相の2相共存相を形成し得る仕事関数差となっている。

4. 发明专利

JP3650005B2 Non-volatile random access memory and a method of manufacturing the same 有权
公开(公告)号：JP3650005B2
公开(公告)日：2005-05-18
申请号：JP2000242127
申请日：2000-08-10
申请人：シャープ株式会社
发明人：茂夫大西 , 数也石原
IPC分类号： H01L27/105 , H01L21/8246
摘要： PROBLEM TO BE SOLVED: To prevent a ferroelectric film from deteriorating and releasing, without bringing the ferroelectric film into contact with an interlayer insulating film such as a SiO2 or the like, and obtain a highly by reliable capacitor, and enhance reliability in FRAM itself. SOLUTION: A memory in chides a MOS transistor, having a gate insulated film 2, a gate electrode 3 a pair of diffusion layers 4, formed on a semiconductor substrate 1; and a ferroelectric capacitor having a lower electrode 7 connected to one diffusion layer 4 of MOS transistor, a ferroelectric film 8 formed only on the lower electrode 7 and an upper electrode 11, and sidewalls of at least the lower electrode 7 and the ferroelectric film 8 are coated with a lamination film of a diffusion prevention film 9 and a SiO2 film 10, and the ferroelectric film 8 comes into contact with the upper electrode 11 on the upper surface of the ferroelerctric film 8, and the other diffusion layer 4 of the MOS transistors is connected to a bit line 13, and the gate electrode 4 is connected to a word line, and the upper electrode 11 of the ferroelectric capacitor is constituted as a drove line.

5. 发明专利

JP3542704B2 Semiconductor memory device 失效
公开(公告)号：JP3542704B2
公开(公告)日：2004-07-14
申请号：JP29235497
申请日：1997-10-24
申请人：シャープ株式会社 , 原徹
发明人：原　　徹 , 茂夫大西 , 俊御手洗
IPC分类号： G11C11/22 , H01L21/02 , H01L21/768 , H01L21/8242 , H01L21/8246 , H01L21/8247 , H01L27/10 , H01L27/105 , H01L27/108 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L21/7687 , H01L27/1085 , H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/60 , H01L28/75
摘要： There is provided a semiconductor memory device with extremely less deterioration of characteristics of dielectric thin film and with high stability. A TaSiN barrier metal layer 13 is formed on a Pt upper electrode 12. This TaSiN barrier metal layer 13 has electrical conductivity and hydrogen-gas blocking property and besides has an amorphous structure stable in high temperature region without crystallizing even during firing for crystallization of an oxide ferroelectric thin film (SBT thin film) 11. Then, hydrogen gas generated during later formation of a second interlayer insulating film 15 is reliably blocked from invading into the oxide ferroelectric thin film 11, by which characteristic deterioration of the oxide ferroelectric thin film 11 due to hydrogen gas is prevented.

6. 发明专利

JP3388089B2 Method of manufacturing a non-volatile semiconductor memory device 失效
公开(公告)号：JP3388089B2
公开(公告)日：2003-03-17
申请号：JP10542196
申请日：1996-04-25
申请人：シャープ株式会社
发明人：茂夫大西 , 淳工藤 , 多賀雄木下
IPC分类号： H01L21/8247 , C23F4/00 , H01L21/02 , H01L21/3213 , H01L21/822 , H01L21/8242 , H01L21/8246 , H01L27/04 , H01L27/10 , H01L27/105 , H01L27/108 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11502 , C23F4/00 , H01L21/32135 , H01L28/60
摘要： A process for fabricating a nonvolatile semiconductor memory device has one transistor and one ferroelectric capacitor electrically connected to each other by a contact plug, which comprising forming a transistor; forming an inter-layer insulating film, at least an upper surface portion thereof being a titanium oxide film; forming a capacitor lower electrode; and forming a capacitor insulating film and a capacitor upper electrode, wherein the lower electrode forming step comprises: depositing a titanium nitride film and a platinum film on the titanium oxide film; etching the platinum film with a first etching gas adapted to suppress deposition of substances including platinum; and etching the titanium nitride film with a second etching gas having a high etching selectivity to the titanium oxide film.

8. 发明专利

JP4088323B1 Non-volatile semiconductor memory device 有权
公开(公告)号：JP4088323B1
公开(公告)日：2008-05-21
申请号：JP2006330045
申请日：2006-12-06
申请人：シャープ株式会社
发明人：剛至井上 , 茂夫大西 , 信義粟屋 , 康成細井
IPC分类号： G11C13/00 , H01L27/10 , H01L45/00 , H01L49/00
CPC分类号： G11C13/0007 , G11C13/0026 , G11C13/0038 , G11C13/0069 , G11C2013/009 , G11C2213/15 , G11C2213/32 , G11C2213/34 , G11C2213/72 , G11C2213/77 , G11C2213/79 , H01L27/101 , H01L27/1021 , H01L27/2409 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/1633
摘要： Provided is a nonvolatile semiconductor device capable of performing writing operations of different resistance changes for memory cells having variable resistive elements whose resistive characteristics are changed by voltage applications, individually and simultaneously. The device includes: a load resistive characteristic variable circuit for each bit line connected commonly with the memory cells on the same column for selecting one of two load resistive characteristics according to a first writing operation where the resistive characteristics of the variable resistive element to be written transit from a low resistance state to a high resistance state or a second writing operation where they transit reversely; and a writing voltage pulse application circuit for applying a first voltage pulse in a first writing operation and a second voltage pulse in a second writing operation to the memory cells to be written through the load resistive characteristic variable circuits and the bit limes.

9. 发明专利

JP3717383B2 Etching method of the ferroelectric film 有权
公开(公告)号：JP3717383B2
公开(公告)日：2005-11-16
申请号：JP2000255028
申请日：2000-08-25
申请人：シャープ株式会社
发明人：茂夫大西 , 恵三崎山 , 淳工藤 , 仁浦島
IPC分类号： H01L21/302 , H01L21/3065 , H01L41/332 , H01L41/39 , H01L41/24

10. 发明专利

JP5120967B2 Variable resistive element 有权
公开(公告)号：JP5120967B2
公开(公告)日：2013-01-16
申请号：JP2009296280
申请日：2009-12-25
申请人：シャープ株式会社 , 独立行政法人産業技術総合研究所
发明人：幸夫玉井 , 康成細井 , 信義粟屋 , 茂夫大西 , 数也石原 , 久島 , 史好高野 , 広幸秋永
IPC分类号： H01L27/105 , H01L45/00 , H01L49/00

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