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1. 发明授权

US08828868B2 Method for forming hard mask in semiconductor device fabrication 有权
标题翻译：在半导体器件制造中形成硬掩模的方法
公开(公告)号：US08828868B2
公开(公告)日：2014-09-09
申请号：US13314000
申请日：2011-12-07
申请人： Zhongshan Hong
发明人： Zhongshan Hong
IPC分类号： H01L21/033 , H01L21/3213
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/28132 , H01L21/32139
摘要： A method for forming a hard mask in semiconductor device fabrication comprises: forming first and second patterned material layers on a third material layer, the second patterned material layer only covering the top of predetermined regions of the first patterned material layer; changing a property of exposed top and side portions of the first patterned material layer using the second patterned material layer as a mask, forming property-changed roofs at the exposed top portions of the first patterned material layer and forming property-changed sidewalls with a predetermined width at the exposed side portions of the first patterned material layer; removing the second patterned material layer and portions of the first patterned material layer with exposed tops and an unchanged property located between the property-changed sidewalls, to form the hard mask.
摘要翻译：在半导体器件制造中形成硬掩模的方法包括：在第三材料层上形成第一和第二图案化材料层，第二图案化材料层仅覆盖第一图案化材料层的预定区域的顶部; 使用第二图案化材料层作为掩模改变第一图案化材料层的暴露的顶部和侧部的性质，在第一图案化材料层的暴露的顶部部分形成特性改变的屋顶，并以预定的宽度在第一图案化材料层的暴露侧部分; 用暴露的顶部去除第二图案化材料层和第一图案化材料层的部分，以及位于属性变化的侧壁之间的不变特性，以形成硬掩模。

2. 发明授权

US08435900B2 Method for manufacturing a transistor 有权
标题翻译：制造晶体管的方法
公开(公告)号：US08435900B2
公开(公告)日：2013-05-07
申请号：US13243977
申请日：2011-09-23
申请人： Qun Shao , Zhongshan Hong
发明人： Qun Shao , Zhongshan Hong
IPC分类号： H01L21/331 , H01L21/461
CPC分类号： H01L21/823412 , H01L21/31053 , H01L21/31056 , H01L21/823456 , H01L21/823468
摘要： The invention provides a method for manufacturing a transistor which includes: providing a substrate having a plurality of transistors formed thereon, wherein each transistor includes a gate; forming a stressed layer and a first oxide layer on the transistors and on the substrate successively; forming a sacrificial layer on the first oxide layer; patterning the sacrificial layer to remove a part of the sacrificial layer which covers on the gates of the transistors; forming a second oxide layer on the residual sacrificial layer and on a part of the first oxide layer which is exposed after the part of the sacrificial layer is removed; performing a first planarization process to remove a part of the second oxide layer located on the gates of the transistors; performing a second planarization process to remove the residual second oxide layer; and performing a third planarization process to remove the stressed layer.
摘要翻译：本发明提供了一种制造晶体管的方法，包括：提供其上形成有多个晶体管的衬底，其中每个晶体管包括栅极; 依次在晶体管和基板上形成应力层和第一氧化物层; 在所述第一氧化物层上形成牺牲层; 图案化牺牲层以去除覆盖在晶体管的栅极上的牺牲层的一部分; 在所述牺牲层的所述部分被去除之后，在所述残留牺牲层上和所述第一氧化物层的一部分上暴露的第二氧化物层; 执行第一平坦化处理以去除位于晶体管的栅极上的第二氧化物层的一部分; 执行第二平坦化处理以去除残留的第二氧化物层; 并执行第三平面化处理以去除应力层。

3. 发明申请

US20130037858A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130037858A1
公开(公告)日：2013-02-14
申请号：US13316217
申请日：2011-12-09
申请人： ZHONGSHAN HONG , Huojin Tu
发明人： ZHONGSHAN HONG , Huojin Tu
IPC分类号： H01L29/165 , H01L21/20
CPC分类号： H01L29/165 , H01L21/02381 , H01L21/0243 , H01L21/0245 , H01L21/0251 , H01L21/02532 , H01L21/0262 , H01L29/66636 , H01L29/7848
摘要： This invention relates to a semiconductor device and a manufacturing method thereof for reducing stacking faults caused by high content of Ge in an embedded SiGe structure. The semiconductor device comprises a Si substrate with a recess formed therein. A first SiGe layer having a Ge content gradually increased from bottom to top is formed on the recess bottom, a SiGe seed layer is formed on sidewalls of the recess and a second SiGe layer having a constant content of Ge is formed on the first SiGe layer. The thickness of the first SiGe layer is less than the depth of the recess. The Ge content in the SiGe seed layer is less than the Ge content in the second SiGe layer and the Ge content at the upper surface of the first SiGe layer is less than or equal to the Ge content in the second SiGe layer.
摘要翻译：本发明涉及一种用于在嵌入式SiGe结构中减少Ge含量高的堆垛层错的半导体器件及其制造方法。半导体器件包括其中形成有凹部的Si衬底。在凹部底部形成具有从底部到顶部逐渐增加的Ge含量的第一SiGe层，在凹槽的侧壁上形成SiGe晶种层，并且在第一SiGe层上形成具有恒定Ge含量的第二SiGe层。第一SiGe层的厚度小于凹槽的深度。 SiGe种子层中的Ge含量小于第二SiGe层中的Ge含量，并且第一SiGe层的上表面处的Ge含量小于或等于第二SiGe层中的Ge含量。

4. 发明申请

US20120295441A1 METHOD FOR FORMING HARD MASK IN SEMICONDUCTOR DEVICE FABRICATION 有权
标题翻译：在半导体器件制造中形成硬掩模的方法
公开(公告)号：US20120295441A1
公开(公告)日：2012-11-22
申请号：US13314000
申请日：2011-12-07
申请人： ZHONGSHAN HONG
发明人： ZHONGSHAN HONG
IPC分类号： H01L21/28 , H01L21/308
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/28132 , H01L21/32139
摘要： A method for forming a hard mask in semiconductor device fabrication comprises: forming first and second patterned material layers on a third material layer, the second patterned material layer only covering the top of predetermined regions of the first patterned material layer; changing a property of exposed top and side portions of the first patterned material layer using the second patterned material layer as a mask, forming property-changed roofs at the exposed top portions of the first patterned material layer and forming property-changed sidewalls with a predetermined width at the exposed side portions of the first patterned material layer; removing the second patterned material layer and portions of the first patterned material layer with exposed tops and an unchanged property located between the property-changed sidewalls, to form the hard mask.
摘要翻译：在半导体器件制造中形成硬掩模的方法包括：在第三材料层上形成第一和第二图案化材料层，第二图案化材料层仅覆盖第一图案化材料层的预定区域的顶部; 使用第二图案化材料层作为掩模改变第一图案化材料层的暴露的顶部和侧部的性质，在第一图案化材料层的暴露的顶部部分形成特性改变的屋顶，并以预定的宽度在第一图案化材料层的暴露侧部分; 用暴露的顶部去除第二图案化材料层和第一图案化材料层的部分，以及位于属性变化的侧壁之间的不变特性，以形成硬掩模。

5. 发明授权

US08951883B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08951883B2
公开(公告)日：2015-02-10
申请号：US13345409
申请日：2012-01-06
申请人： Qun Shao , Zhongshan Hong
发明人： Qun Shao , Zhongshan Hong
IPC分类号： H01L21/76 , H01L21/762
CPC分类号： H01L21/76229
摘要： A semiconductor device and a manufacturing method therefor is based on the fact that a thinner liner oxide layer on the bottom of the trenches can lead to a higher subsequent deposition rate. After forming trenches and a liner oxide layer and before depositing a filling oxide layer in the trenches, a portion of or all of the thickness of the liner oxide layer on bottom of trenches in an isolation area is removed. Removing some or all of a liner oxide layer on the bottom of trenches in an isolation area can improve the deposition rate for trenches in such that the difference in thickness can be reduced for deposited filling oxide layer between isolation area and dense area.
摘要翻译：半导体器件及其制造方法基于以下事实：沟槽底部的较薄的衬垫氧化物层可导致更高的后续沉积速率。在形成沟槽和衬里氧化物层之后并且在沟槽中沉积填充氧化物层之前，在隔离区域中的沟槽底部的衬里氧化物层的厚度的一部分或全部被去除。在隔离区域中去除沟槽底部的一部分或全部衬垫氧化物层可以提高沟槽的沉积速率，从而可以减小隔离区域和密集区域之间沉积的填充氧化物层的厚度差。

6. 发明授权

US08802523B2 CMOS device and fabrication method 有权
标题翻译： CMOS器件及其制造方法
公开(公告)号：US08802523B2
公开(公告)日：2014-08-12
申请号：US13675216
申请日：2012-11-13
申请人： Zhongshan Hong
发明人： Zhongshan Hong
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L21/8238 , H01L21/26506 , H01L21/823842 , H01L27/092 , H01L29/4966 , H01L29/513 , H01L29/66545 , H01L29/78 , H01L29/7848
摘要： Various embodiments provide complementary metal-oxide-semiconductor (CMOS) devices and fabrication methods. An exemplary CMOS device can be formed by providing a first dummy gate over a semiconductor substrate in a first region, providing a second dummy gate over the semiconductor substrate in a second region, and amorphizing a surface portion of the first dummy gate to form a first amorphous silicon layer. The first amorphous silicon layer can be used to protect the first dummy gate in the first region, when a second opening is formed in the second region by wet etching at least the second dummy gate. A second metal gate can then be formed in the second opening, followed by removing the first amorphous silicon layer and at least the first dummy gate to form a first opening in the first region. A first metal gate can be formed in the first opening.
摘要翻译：各种实施例提供互补的金属氧化物半导体（CMOS）器件和制造方法。可以通过在第一区域中的半导体衬底上提供第一虚拟栅极来形成示例性CMOS器件，在第二区域中在半导体衬底上提供第二虚拟栅极，并且使第一虚拟栅极的表面部分非晶化，以形成第一非晶硅层。当通过至少第二虚拟栅极湿蚀刻在第二区域中形成第二开口时，第一非晶硅层可用于保护第一区域中的第一伪栅极。然后可以在第二开口中形成第二金属栅极，随后去除第一非晶硅层和至少第一伪栅极以在第一区域中形成第一开口。可以在第一开口中形成第一金属栅极。

7. 发明授权

US08697575B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08697575B2
公开(公告)日：2014-04-15
申请号：US13307766
申请日：2011-11-30
申请人： Zhongshan Hong
发明人： Zhongshan Hong
IPC分类号： H01L21/44
CPC分类号： H01L21/76898 , H01L24/05 , H01L2924/13091 , H01L2924/00
摘要： The present invention relates to a semiconductor device and the manufacturing method thereof. First, a hole is formed on a first side of a substrate. Then, an isolation layer is formed on an inner side of the hole and the hole is filled with a semiconductor material. Next, functional structures are formed on the first side of the substrate, the substrate is thinned from its second side opposite to the first side to expose the semiconductor material in the hole, and then the semiconductor material in the hole is removed to form a through hole penetrating through the substrate. The through hole is filled with a conductive material, thereby obtaining a final through substrate via (TSV) for facilitating electrical connection between different chips. By using a semiconductor material as TSV dummy material before filling the TSV with metal, the method can be better compatible with the standard process flow.
摘要翻译：半导体器件及其制造方法技术领域本发明涉及半导体器件及其制造方法。首先，在基板的第一面上形成孔。然后，在孔的内侧形成隔离层，并且填充有半导体材料。接下来，在基板的第一面上形成功能结构，从与第一侧相反的第二侧减薄基板，露出孔内的半导体材料，然后去除孔内的半导体材料，形成通孔穿透衬底的孔。通孔填充有导电材料，从而获得最终通过衬底通孔（TSV），以促进不同芯片之间的电连接。通过在用金属填充TSV之前使用半导体材料作为TSV虚拟材料，该方法可以更好地与标准工艺流程兼容。

8. 发明申请

US20130146989A1 INTEGRATED SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR 有权
标题翻译：集成半导体器件及其制造方法
公开(公告)号：US20130146989A1
公开(公告)日：2013-06-13
申请号：US13418339
申请日：2012-03-12
申请人： ZHONGSHAN HONG
发明人： ZHONGSHAN HONG
IPC分类号： H01L27/06 , H01L21/283
CPC分类号： H01L27/0629 , H01L27/0802 , H01L28/24
摘要： An integrated device includes a field effect transistor formed within and upon an active region of a substrate and a resistor formed on an isolation region of the substrate. The field effect transistor includes a gate stacked structure having respective portions of a dielectric layer, a first conductive layer and a second conductive layer arranged in order from bottom to top. The resistor includes a resistor body being an enclosure portion of the first conductive layer and resistor terminals being portions of the second conductive layer on distal ends of the resistor body. A method for manufacturing a semiconductor device includes forming a gate stacked structure and a resistor stacked structure at the same time by patterning a dielectric layer, a first conductive layer and a second conductive layer. The method also includes forming a resistor having a resistor body by patterning the resistor stacked structure.
摘要翻译：集成器件包括形成在衬底的有源区内和之上的场效应晶体管，以及形成在衬底的隔离区上的电阻器。场效应晶体管包括栅层叠结构，其具有电介质层的相应部分，第一导电层和第二导电层，从底部到顶部依次布置。电阻器包括电阻器体，其是第一导电层的封闭部分，电阻器端子是电阻体的远端上的第二导电层的部分。一种制造半导体器件的方法包括通过图案化介电层，第一导电层和第二导电层同时形成栅叠层结构和电阻堆叠结构。该方法还包括通过图案化电阻器堆叠结构来形成具有电阻体的电阻器。

9. 发明授权

US08379183B2 LCOS display unit and method for forming the same 有权
标题翻译： LCOS显示单元及其形成方法
公开(公告)号：US08379183B2
公开(公告)日：2013-02-19
申请号：US13155870
申请日：2011-06-08
申请人： Herb He Huang , Xianyong Pu , Jianhong Mao , Yiqun Chen , Jing Fu , Zhongshan Hong , Yanghui Xiang
发明人： Herb He Huang , Xianyong Pu , Jianhong Mao , Yiqun Chen , Jing Fu , Zhongshan Hong , Yanghui Xiang
IPC分类号： G02F1/13 , G02F1/1335
CPC分类号： G02F1/136277 , G02F1/133553 , G02F1/136209 , H01L27/12 , H01L27/1214 , H01L27/13 , H01L29/78633 , H01L29/78654
摘要： An embodiment of the present invention discloses a Liquid Crystal on Silicon (LCOS) display unit, in which a Metal-Insulator-Metal (MIM) capacitor consisting of a micromirror layer, a insulation layer and a light shielding layer is formed by grounding the light shielding layer on a pixel switch circuit layer. Therefore the pixel switch circuit and the capacitor are in vertical distribution, that is, the switch circuit and the capacitor both have an allowable design area of the size of one pixel. Another embodiment of the present invention provides a method for forming a Liquid Crystal on Silicon (LCOS) display unit.
摘要翻译：本发明的实施例公开了一种液晶硅（LCOS）显示单元，其中通过将光接地而形成由微镜层，绝缘层和遮光层组成的金属 - 绝缘体 - 金属（MIM）电容器像素开关电路层上的屏蔽层。因此，像素开关电路和电容器处于垂直分布，即开关电路和电容器都具有允许的一个像素尺寸的设计区域。本发明的另一个实施例提供了一种用于形成硅晶体（LCOS）显示单元的方法。

10. 发明授权

US08349675B2 Method for forming a gate electrode 有权
标题翻译：栅电极形成方法
公开(公告)号：US08349675B2
公开(公告)日：2013-01-08
申请号：US13177517
申请日：2011-07-06
申请人： Zhongshan Hong
发明人： Zhongshan Hong
IPC分类号： H01L21/338
CPC分类号： H01L29/66545 , H01L21/28079 , H01L21/28114 , H01L29/42376 , H01L29/495 , H01L29/517
摘要： A method for forming a gate electrode includes: providing a substrate; forming a gate dielectric layer and forming a sacrificial layer, the sacrificial layer including doping ions, a density of the doping ions in the sacrificial layer decreasing with increasing distance from the substrate; forming a hard mask layer; patterning the sacrificial layer and the hard mask layer; removing part of the patterned sacrificial layer by wet etching with the patterned hard mask layer as a mask, to form a dummy gate electrode which has a top width bigger than a bottom width, and removing the patterned hard mask layer; removing the dummy gate electrode and filling a gate trench with gate material to form a gate electrode which has a top width bigger than a bottom width, which facilitates the filling of the gate material and can avoid or reduce cavity forming in the gate material.
摘要翻译：一种形成栅电极的方法包括：提供衬底; 形成栅介电层并形成牺牲层，所述牺牲层包括掺杂离子，所述牺牲层中的掺杂离子的密度随着距衬底的距离的增加而减小; 形成硬掩模层; 图案化牺牲层和硬掩模层; 通过用图案化的硬掩模层作为掩模的湿蚀刻去除图案化的牺牲层的一部分，以形成顶部宽度大于底部宽度的虚拟栅电极，并且去除图案化的硬掩模层; 去除虚拟栅电极并用栅极材料填充栅极沟槽以形成具有大于底部宽度的顶部宽度的栅电极，这有助于栅极材料的填充并且可以避免或减少栅极材料中的空腔形成。

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