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1. 发明申请

US20120023349A1 INFORMATION PROCESSING APPARATUS AND POWER SAVING MEMORY MANAGEMENT METHOD 失效
标题翻译：信息处理设备和节电存储管理方法
公开(公告)号：US20120023349A1
公开(公告)日：2012-01-26
申请号：US13187249
申请日：2011-07-20
申请人： Shinichi MACHIDA , Satoshi OGUNI , Susumu KAJITA , Yuko ISHIBASHI , Hitoshi UENO
发明人： Shinichi MACHIDA , Satoshi OGUNI , Susumu KAJITA , Yuko ISHIBASHI , Hitoshi UENO
IPC分类号： G06F1/32 , G06F1/26
CPC分类号： G06F1/3203 , G06F1/26 , G06F1/3275 , Y02D10/13 , Y02D10/14
摘要： An information processing apparatus has a task area unit as an area that executes a predetermined process, a power control unit that reads a task area to execute the process from the process and supplies power from a power source to the read task area, and a control unit that executes the process in the task area unit to which the power is supplied by the power control unit.
摘要翻译：信息处理装置具有作为执行预定处理的区域的任务区域单元，从该处理读取执行处理的任务区域并将电力从电源提供给读取任务区域的电力控制单元，以及控制单元，其执行由功率控制单元提供电力的任务区单元中的处理。

2. 发明授权

US08745426B2 Information processing apparatus and power saving memory management method with an upper limit of task area units that may be simultaneously powered 失效
标题翻译：具有同时供电的任务区域单元的上限的信息处理装置和省电存储器管理方法
公开(公告)号：US08745426B2
公开(公告)日：2014-06-03
申请号：US13187249
申请日：2011-07-20
申请人： Shinichi Machida , Satoshi Oguni , Susumu Kajita , Yuko Ishibashi , Hitoshi Ueno
发明人： Shinichi Machida , Satoshi Oguni , Susumu Kajita , Yuko Ishibashi , Hitoshi Ueno
IPC分类号： G06F1/26 , G06F1/32 , G06F1/00 , G06F13/00 , G06F13/28
CPC分类号： G06F1/3203 , G06F1/26 , G06F1/3275 , Y02D10/13 , Y02D10/14
摘要： An information processing apparatus has a task area unit as an area that executes a predetermined process, a power control unit that reads a task area to execute the process from the process and supplies power from a power source to the read task area, and a control unit that executes the process in the task area unit to which the power is supplied by the power control unit.
摘要翻译：信息处理装置具有作为执行预定处理的区域的任务区域单元，从该处理读取执行处理的任务区域并将电力从电源提供给读取任务区域的电力控制单元，以及控制单元，其执行由功率控制单元提供电力的任务区单元中的处理。

3. 发明授权

US5968135A Processing instructions up to load instruction after executing sync flag monitor instruction during plural processor shared memory store/load access synchronization 失效
标题翻译：在多个处理器共享存储器/负载访问同步期间执行同步标志监视指令之后，处理指令，直到加载指令
公开(公告)号：US5968135A
公开(公告)日：1999-10-19
申请号：US972539
申请日：1997-11-18
申请人： Yasuhiro Teramoto , Toshimitsu Andoh , Tadaaki Isobe , Naonobu Sukegawa , Yuko Ishibashi
发明人： Yasuhiro Teramoto , Toshimitsu Andoh , Tadaaki Isobe , Naonobu Sukegawa , Yuko Ishibashi
IPC分类号： G06F9/38 , G06F9/30 , G06F9/46 , G06F9/52 , G06F15/16 , G06F15/177 , G06F15/167
CPC分类号： G06F9/52
摘要： An information processing system is connected to a common storage and executes programs by use of processors. This system includes a common storage; a plurality of processors, connected to the common storage. Each processor executes an instruction to store data from common storage, and an instruction to load data from the common storage into the cache storage, wherein each processor includes a communication controller for, when detecting synchronization completion information for attaining synchronization of execution of instructions among a plurality of processors, sending synchronization completion information and receiving synchronization information from another processor; an instruction executing section for detecting a specified change of the flag of a specified location in the common storage by executing a Monitor instruction included in a program in response to synchronization information from the communication controller; an execution controller to execute subsequent instructions after the Monitor instruction, exclusive of a Load instruction to load data into a cache storage, until a change of the flag is detected by the execution section, wherein the processor allows instruction for loading data from common storage into the cache storage to be executed after the flag detection, and wherein the execution controller may include an inhibit resetting circuit to issue an inhibit instruction control signal to terminate the instruction send-out inhibiting action of the instruction inhibit circuit according to input from a service processor.
摘要翻译：信息处理系统连接到公共存储器，并通过使用处理器执行程序。该系统包括一个通用存储器; 连接到公共存储器的多个处理器。每个处理器执行用于存储来自公共存储器的数据的指令，以及用于将数据从公共存储器加载到高速缓存存储器中的指令，其中每个处理器包括通信控制器，用于当检测到同步完成信息以实现指令的执行同步时多个处理器，发送同步完成信息和从另一处理器接收同步信息; 指令执行部分，用于响应于来自通信控制器的同步信息，通过执行包括在程序中的监视指令来检测公共存储器中的指定位置的标志的指定变化; 执行控制器，用于执行监视器指令之后的后续指令，不包括将数据加载到高速缓存存储器中的加载指令，直到所述执行部分检测到所述标志的改变，其中所述处理器允许从共同存储器加载数据的指令所述高速缓存存储器在所述标志检测之后执行，并且其中所述执行控制器可以包括禁止复位电路，以发出禁止指令控制信号，以根据来自服务处理器的输入来终止所述指令禁止电路的指令发送禁止动作。

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