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1. 发明授权

US07609805B2 Mask used for LIGA process, method of manufacturing the mask, and method of manufacturing microstructure using LIGA process 有权
标题翻译：用于LIGA工艺的掩模，制造掩模的方法以及使用LIGA工艺制造微结构的方法
公开(公告)号：US07609805B2
公开(公告)日：2009-10-27
申请号：US11896273
申请日：2007-08-30
申请人： Chan-wook Baik , Yong-wan Jin , Gun-sik Park , Jong-min Kim , Young-min Shin , Jin-kyu So
发明人： Chan-wook Baik , Yong-wan Jin , Gun-sik Park , Jong-min Kim , Young-min Shin , Jin-kyu So
IPC分类号： G21K5/00
CPC分类号： G03F7/00 , G03F1/22 , G03F9/7053 , G03F9/7076
摘要： A mask used for a Lithographie, Galvanofomung, and Abformung (LIGA) process, a method for manufacturing the mask, and a method for manufacturing a microstructure using a LIGA process. The method for manufacturing the microstructure using the LIGA process contemplates forming a substrate for the microstructure, a plurality of photosensitive layers, each photosensitive layer having a plating hole and an aligning pinhole, and an aligning pin capable of being inserted into the aligning pinhole, with the aligning pinholes of the photosensitive layers being formed in corresponding positions, and repeating a process of stacking the photosensitive layer on the substrate for the microstructure and a process of forming a plating layer by plating the plating hole of the stacked photosensitive layer with a metal for a number of times corresponding to the number of the photosensitive layers, and when the photosensitive layers are stacked on the substrate for the structure, the photosensitive layers being aligned with one another by inserting the aligning pin into the aligning pinholes of all the photosensitive layers stacked on the substrate for the microstructure to penetrate all the photosensitive layers.
摘要翻译：用于石版印刷，Galvanofomung和Abformung（LIGA）工艺的掩模，用于制造掩模的方法以及使用LIGA工艺制造微结构的方法。使用LIGA方法制造微结构的方法考虑形成用于微结构的基底，多个感光层，每个感光层具有电镀孔和对准针孔，以及能够插入到对准针孔中的对准销，感光层的对准针孔形成在相应的位置上，并且重复将用于微结构的基板上的感光层层叠的工艺和通过用金属镀覆层叠的感光层的电镀孔来形成镀层的工艺对应于感光层的数量的次数，并且当感光层堆叠在用于结构的基板上时，感光层通过将对准销插入到所有感光层的对准针孔中而彼此对准在基板上用于微结构穿透感光层。

2. 发明申请

US20090096378A1 Traveling-Wave Tube 2D Slow Wave Circuit 有权
标题翻译：行波管2D慢波电路
公开(公告)号：US20090096378A1
公开(公告)日：2009-04-16
申请号：US12248019
申请日：2008-10-08
申请人： Larry R. Barnett , Young-Min Shin
发明人： Larry R. Barnett , Young-Min Shin
IPC分类号： H01J25/34
CPC分类号： H01J25/34 , H01J23/20
摘要： A two-dimensional circuit for a traveling-wave tube for millimeter and sub-millimeter electromagnetic waves synchronously interacts with an electron beam in a vacuum electronic microwave amplifier or oscillator. The circuit is a solid body having a length along the tube axis. The solid body has an electrically conductive top section and an electrically conductive bottom section. The top section is configured with a plurality of vertical vanes having a width and height and configured parallel to each other. The bottom section is similarly configured such that when the circuit is viewed in cross section along the length, the vanes on the bottom section are staggered with respect to the vanes on the top section. The top section and the bottom section are separated from each other to define a tunnel through the solid body along the length.
摘要翻译：用于毫米和亚毫米电磁波的行波管的二维电路与真空电子微波放大器或振荡器中的电子束同步地相互作用。该电路是具有沿着管轴长度的固体。固体具有导电顶部和导电底部。顶部构造有具有宽度和高度的多个垂直叶片并且彼此平行配置。底部部分类似地构造成使得当沿着长度的横截面观察回路时，底部部分上的叶片相对于顶部部分上的叶片交错。顶部部分和底部部分彼此分离以沿着长度限定通过固体的隧道。

3. 发明授权

US07320098B2 Semiconductor integrated circuit device having scan flip-flop circuit 有权
标题翻译：具有扫描触发电路的半导体集成电路器件
公开(公告)号：US07320098B2
公开(公告)日：2008-01-15
申请号：US11122382
申请日：2005-05-05
申请人： Young-Min Shin
发明人： Young-Min Shin
IPC分类号： G01R31/28
CPC分类号： G01R31/318552 , G01R31/318541 , G01R31/318583
摘要： A semiconductor integrated circuit device has a normal operation mode and a scan test operation mode, and includes a pulse generating circuit and a scan flip-flop circuit. The pulse generating circuit generates pulse signals synchronized with a clock signal in each of the normal and scan test operation modes. The scan flip-flop circuit latches data in response to the pulse signals from the pulse generating circuit signal in each of the normal and scan test operation modes.
摘要翻译：半导体集成电路器件具有正常操作模式和扫描测试操作模式，并且包括脉冲发生电路和扫描触发器电路。在每个正常和扫描测试操作模式中，脉冲发生电路产生与时钟信号同步的脉冲信号。扫描触发器电路在每个正常和扫描测试操作模式中响应于来自脉冲发生电路信号的脉冲信号来锁存数据。

4. 发明授权

US07893718B2 High-speed multiplexer and semiconductor device including the same 有权
标题翻译：高速多路复用器和包括相同的半导体器件
公开(公告)号：US07893718B2
公开(公告)日：2011-02-22
申请号：US12540465
申请日：2009-08-13
申请人： Sung Bae Park , Gun Ok Jung , Young Min Shin , Hoi Jin Lee , Chang Jun Choi , Min Su Kim
发明人： Sung Bae Park , Gun Ok Jung , Young Min Shin , Hoi Jin Lee , Chang Jun Choi , Min Su Kim
IPC分类号： H03K19/094
CPC分类号： H03K19/1737 , H03K17/005 , H03K17/693 , H03K19/0013 , H03K2217/0036
摘要： High speed multiplexers include a first N-to-1 selection circuit, where N is an integer greater than one, a second N-to-1 selection circuit and an output driver. The first N-to-1 selection circuit is configured to route a true or complementary version of a selected first input signal (from amongst N input signals) to an output thereof in response to a first multi-bit selection signal, where N is an integer greater than one. The second N-to-1 selection circuit is configured to route a true or complementary version of the selected first input signal to an output thereof in response to a second multi-bit selection signal. The output driver includes a pull-up circuit, which is responsive to a signal generated at the output of the first N-to-1 selection circuit, and a pull-down circuit, which is responsive to a signal generated at the output of the second N-to-1 selection circuit.
摘要翻译：高速多路复用器包括第一N-1选择电路，其中N是大于1的整数，第二N-1选择电路和输出驱动器。第一N-1选择电路被配置为响应于第一多位选择信号将所选择的第一输入信号（从N个输入信号中）的真或互补版本路由到其输出，其中N是大于1的整数。第二N-1选择电路被配置为响应于第二多位选择信号将所选择的第一输入信号的真实或互补版本路由到其输出。输出驱动器包括上拉电路，其响应于在第一N-1选择电路的输出处产生的信号，以及下拉电路，其响应于在输出端产生的信号第二个N到1选择电路。

5. 发明申请

US20050268191A1 Semiconductor integrated circuit device having scan flip-flop circuit 有权
标题翻译：具有扫描触发电路的半导体集成电路器件
公开(公告)号：US20050268191A1
公开(公告)日：2005-12-01
申请号：US11122382
申请日：2005-05-05
申请人： Young-Min Shin
发明人： Young-Min Shin
IPC分类号： G01R31/26 , G01R31/28 , G01R31/3185 , H03K19/00
CPC分类号： G01R31/318552 , G01R31/318541 , G01R31/318583
摘要： Asemiconductor integrated circuit devices has a normal operation mode and a scan test operation mode, and includes a pulse generating circuit and a scan flip-flop circuit. The pulse generating circuit generates pulse signals synchronized with a clock signal in each of the normal and scan test operation modes. The scan flip-flop circuit latches data in response to the pulse signals from the pulse generating circuit signal in each of the normal and scan test operation modes.
摘要翻译：半导体集成电路器件具有正常操作模式和扫描测试操作模式，并且包括脉冲发生电路和扫描触发器电路。在每个正常和扫描测试操作模式中，脉冲发生电路产生与时钟信号同步的脉冲信号。扫描触发器电路在每个正常和扫描测试操作模式中响应于来自脉冲发生电路信号的脉冲信号来锁存数据。

6. 发明申请

US20060125542A1 Point diffusion signal distribution with minimized power consumption and signal skew 有权
标题翻译：点扩散信号分布，功耗和信号偏移最小化
公开(公告)号：US20060125542A1
公开(公告)日：2006-06-15
申请号：US11297004
申请日：2005-12-08
申请人： Gun-Ok Jung , Young-Min Shin
发明人： Gun-Ok Jung , Young-Min Shin
IPC分类号： G06F1/04
CPC分类号： G06F1/10
摘要： For distributing a signal to loads in an area, the area is divided into a plurality of regions. A respective signal point is disposed in each region for providing the signal to a load in the region. A respective diffusion point is disposed between any two neighboring signal points. The signal is initially applied to a center point of the signal and diffusion points. The signal when received at a given signal or diffusion point is transmitted to any of the signal or diffusion points within a maximum distance from the given signal or diffusion point.
摘要翻译：为了将信号分配到区域中的负载，该区域被分成多个区域。相应的信号点设置在每个区域中，用于向该区域中的负载提供信号。相应的扩散点设置在任何两个相邻信号点之间。信号最初被施加到信号和扩散点的中心点。在给定信号或扩散点处接收到的信号被传送到与给定信号或扩散点的最大距离内的任何信号或扩散点。

7. 发明授权

US06577692B1 Clock forwarding circuit with automatic clock delay detection and initial parameter setting features 有权
标题翻译：具有自动时钟延迟检测和初始参数设置功能的时钟转发电路
公开(公告)号：US06577692B1
公开(公告)日：2003-06-10
申请号：US09449147
申请日：1999-11-24
申请人： Young-Min Shin
发明人： Young-Min Shin
IPC分类号： G06F112
CPC分类号： H04L7/0008 , H04L7/0041
摘要： A clock forwarding circuit automatically detects the delay in transmission of data between a master circuit such as a central processing unit and a slave circuit such as a semiconductor memory and forwards clocks corresponding to the delay. The master circuit includes a clock forwarding circuit which generates a clock signal. The slave circuit is coupled to the master circuit and generates a second clock signal which is synchronized with the first clock signal. The clock forwarding circuit receives the second clock signal, detects delay between the first and second clock signals and sets initial data load/unload parameters of the master circuit based on the detected delay. By forwarding clocks, the data transmission between the clocked circuits can be performed in faultless fashion independently of the delay.
摘要翻译：时钟转发电路自动检测诸如中央处理单元的主电路和诸如半导体存储器的从电路之间的数据传输的延迟，并转发与延迟相对应的时钟。主电路包括产生时钟信号的时钟转发电路。从电路耦合到主电路并产生与第一时钟信号同步的第二时钟信号。时钟转发电路接收第二时钟信号，检测第一和第二时钟信号之间的延迟，并基于检测到的延迟设置主电路的初始数据加载/卸载参数。通过转发时钟，时钟电路之间的数据传输可以以无故障的方式独立于延迟来执行。

8. 发明授权

US5654777A Method for controlling display of video data on an LCD and circuit for implementing the same 失效
标题翻译：用于控制LCD上的视频数据的显示和用于实现其的电路的方法
公开(公告)号：US5654777A
公开(公告)日：1997-08-05
申请号：US443284
申请日：1995-05-17
申请人： Young-min Shin
发明人： Young-min Shin
IPC分类号： G02F1/133 , G09G3/20 , G09G3/36 , H04N3/14
CPC分类号： G09G3/3611 , G09G3/3607
摘要： A method for controlling display video data on an LCD panel having a display matrix of pixels arranged in rows and columns and having a delta structure, which includes the steps of displaying the video data in its original (unchanged) form during a first field of the video data, and displaying the video data in a modified form during a second field of the video data, with alternate (e.g., odd-numbered) lines of the video data being shifted one pixel towards a first (e.g., right) side of the display matrix. A control circuit for implementing this method generates first and second control signals for controlling the operation of a column driving circuit which drives the columns of pixels of the display matrix in the appropriate manner.
摘要翻译：一种用于在LCD面板上控制显示视频数据的方法，所述LCD面板具有排列成行和列的像素的显示矩阵并且具有三角形结构，所述方法包括以下步骤：在所述视频数据的第一场期间以其原始（未更改）形式显示所述视频数据视频数据，并且在视频数据的第二场期间以修改的形式显示视频数据，其中视频数据的交替（例如，奇数）行被移动到一个像素的第一（例如，右）一侧显示矩阵。用于实现该方法的控制电路产生用于控制以适当的方式驱动显示矩阵的像素列的列驱动电路的操作的第一和第二控制信号。

9. 发明授权

US08949534B2 Multi-CPU system and computing system having the same 有权
标题翻译：多CPU系统和计算系统具有相同的功能
公开(公告)号：US08949534B2
公开(公告)日：2015-02-03
申请号：US13741717
申请日：2013-01-15
申请人： Hoi Jin Lee , Young Min Shin
发明人： Hoi Jin Lee , Young Min Shin
IPC分类号： G06F12/08 , G06F1/32
CPC分类号： G06F12/0811 , G06F1/3234 , G06F1/3275 , G06F12/0833 , G06F12/084 , G06F2212/1028 , G06F2212/283 , G06F2212/62 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： A multi-CPU data processing system, comprising: a multi-CPU processor, comprising: a first CPU configured with at least a first core, a first cache, and a first cache controller configured to access the first cache; and a second CPU configured with at least a second core, and a second cache controller configured to access a second cache, wherein the first cache is configured from a shared portion of the second cache.
摘要翻译：一种多CPU数据处理系统，包括：多CPU处理器，包括：第一CPU，配置有至少第一内核，第一高速缓存和配置为访问第一高速缓存的第一高速缓存控制器; 以及配置有至少第二核心的第二CPU和被配置为访问第二高速缓存的第二高速缓存控制器，其中所述第一高速缓存由所述第二高速缓存的共享部分配置。

10. 发明申请

US20110155965A1 Polycarbonate Resin Composition Having Excellent Wear Resistance and Electric Conductivity and Method of Preparing the Same 有权
标题翻译：具有优异的耐磨性和导电性的聚碳酸酯树脂组合物及其制备方法
公开(公告)号：US20110155965A1
公开(公告)日：2011-06-30
申请号：US12968426
申请日：2010-12-15
申请人： Young Min Shin , Sang Wan Kim , Young Kyu Chang , Young Sil Lee
发明人： Young Min Shin , Sang Wan Kim , Young Kyu Chang , Young Sil Lee
IPC分类号： H01B1/24 , B82Y30/00
CPC分类号： H01B1/24 , B82Y30/00
摘要： The present invention provides a polycarbonate resin composition comprising a polycarbonate (A), a styrene copolymer resin (B), carbon nano-tubes (C) and a carbon black (D).
摘要翻译：本发明提供包含聚碳酸酯（A），苯乙烯共聚物树脂（B），碳纳米管（C）和炭黑（D）的聚碳酸酯树脂组合物。

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