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1. 发明授权

US06301692B1 Method for designing layout of semiconductor integrated circuit, semiconductor integrated circuit obtained by the same method, and method for verifying timing thereof 失效
标题翻译：用于设计半导体集成电路的布局的方法，通过相同的方法获得的半导体集成电路以及用于验证其定时的方法
公开(公告)号：US06301692B1
公开(公告)日：2001-10-09
申请号：US09153063
申请日：1998-09-15
申请人： Shinichi Kumashiro , Hiroshi Mizuno , Yasuhiro Tanaka , Toshiyuki Moriwaki , Youichirou Mae
发明人： Shinichi Kumashiro , Hiroshi Mizuno , Yasuhiro Tanaka , Toshiyuki Moriwaki , Youichirou Mae
IPC分类号： G06F1750
CPC分类号： G06F17/5022 , G06F17/5068 , H01L27/11807
摘要： First of all, a given logic circuit is divided into a combinational circuit portion and a register portion. The combinational circuit portion obtained by division is divided into a plurality of partial circuits having high connectivity. Each partial circuit is converted into a circuit having the transistor level. Then, a layout cell of the partial circuit having the transistor level is generated. Thereafter, arrangement and wiring are performed by using, as unit cells, a layout cell which corresponds to each register included in the register portion and the layout cell for each partial circuit in the combinational circuit so that a block layout is created. Accordingly, a layout having excellent characteristics can be created by a few kinds of cells in both circuits having the CMOS logic and the pass-transistor logic. In particular, the partial circuits having high connectivity are arranged in a cell in the circuit using the pass-transistor logic. Consequently, the optimum driving capability can be obtained and the layout having stable characteristics can be created. In addition, it is possible to ensure the superiority such as a reduction in area, the low consumed power, high-speed operation and the like.
摘要翻译：首先，将给定逻辑电路分为组合电路部分和寄存器部分。通过划分获得的组合电路部分被分成多个具有高连通性的部分电路。每个部分电路被转换成具有晶体管电平的电路。然后，产生具有晶体管电平的部分电路的布局单元。此后，通过使用与组合电路中的每个部分电路中包括的寄存器部分中的每个寄存器对应的布局单元和组合电路中的每个部分电路的布局单元作为单位单元来执行布置和布线，从而创建块布局。因此，具有优异特性的布局可以通过具有CMOS逻辑和传输晶体管逻辑的两个电路中的几种单元产生。特别地，具有高连通性的部分电路使用传输晶体管逻辑布置在电路中的单元中。因此，可以获得最佳的驱动能力，并且可以产生具有稳定特性的布局。另外，可以确保面积减少，低功耗，高速运转等优点。

2. 发明授权

US5983008A Method for designing layout of semiconductor integrated circuit, semiconductor integrated circuit obtained by the same method, and method for verifying timing thereof 失效
标题翻译：用于设计半导体集成电路的布局的方法，通过相同的方法获得的半导体集成电路以及用于验证其定时的方法
公开(公告)号：US5983008A
公开(公告)日：1999-11-09
申请号：US153333
申请日：1998-09-15
申请人： Shinichi Kumashiro , Hiroshi Mizuno , Yasuhiro Tanaka , Toshiyuki Moriwaki , Youichirou Mae
发明人： Shinichi Kumashiro , Hiroshi Mizuno , Yasuhiro Tanaka , Toshiyuki Moriwaki , Youichirou Mae
IPC分类号： G06F17/50 , H01L27/118
CPC分类号： G06F17/5022 , G06F17/5068 , H01L27/11807
摘要： First of all, a given logic circuit is divided into a combinational circuit portion and a register portion. The combinational circuit portion obtained by division is divided into a plurality of partial circuits having high connectivity. Each partial circuit is converted into a circuit having the transistor level. Then, a layout cell of the partial circuit having the transistor level is generated. Thereafter, arrangement and wiring are performed by using, as unit cells, a layout cell which corresponds to each register included in the register portion and the layout cell for each partial circuit in the combinational circuit so that a block layout is created. Accordingly, a layout having excellent characteristics can be created by a few kinds of cells in both circuits having the CMOS logic and the pass-transistor logic. In particular, the partial circuits having high connectivity are arranged in a cell in the circuit using the pass-transistor logic. Consequently, the optimum driving capability can be obtained and the layout having stable characteristics can be created. In addition, it is possible to ensure the superiority such as a reduction in area, the low consumed power, high-speed operation and the like.
摘要翻译：首先，将给定逻辑电路分为组合电路部分和寄存器部分。通过划分获得的组合电路部分被分成多个具有高连通性的部分电路。每个部分电路被转换成具有晶体管电平的电路。然后，产生具有晶体管电平的部分电路的布局单元。此后，通过使用与组合电路中的每个部分电路中包括的寄存器部分中的每个寄存器对应的布局单元和组合电路中的每个部分电路的布局单元作为单位单元来执行布置和布线，从而创建块布局。因此，具有优异特性的布局可以通过具有CMOS逻辑和传输晶体管逻辑的两个电路中的几种单元产生。特别地，具有高连通性的部分电路使用传输晶体管逻辑布置在电路中的单元中。因此，可以获得最佳的驱动能力，并且可以产生具有稳定特性的布局。另外，可以确保面积减少，低功耗，高速运转等优点。

3. 发明授权

US5923569A Method for designing layout of semiconductor integrated circuit semiconductor integrated circuit obtained by the same method and method for verifying timing thereof 失效
标题翻译：通过用于验证其定时的相同方法和方法获得的半导体集成电路半导体集成电路布局的设计方法
公开(公告)号：US5923569A
公开(公告)日：1999-07-13
申请号：US732808
申请日：1996-10-15
申请人： Shinichi Kumashiro , Hiroshi Mizuno , Yasuhiro Tanaka , Toshiyuki Moriwaki , Youichirou Mae
发明人： Shinichi Kumashiro , Hiroshi Mizuno , Yasuhiro Tanaka , Toshiyuki Moriwaki , Youichirou Mae
IPC分类号： G06F17/50 , H01L27/118
CPC分类号： G06F17/5022 , G06F17/5068 , H01L27/11807
摘要： First of all, a given logic circuit is divided into a combinational circuit portion and a register portion. The combinational circuit portion obtained by division is divided into a plurality of partial circuits having high connectivity. Each partial circuit is converted into a circuit having the transistor level. Then, a layout cell of the partial circuit having the transistor level is generated. Thereafter, arrangement and wiring are performed by using, as unit cells, a layout cell which corresponds to each register included in the register portion and the layout cell for each partial circuit in the combinational circuit so that a block layout is created. Accordingly, a layout having excellent characteristics can be created by a few kinds of cells in both circuits having the CMOS logic and the pass-transistor logic. In particular, the partial circuits having high connectivity are arranged in a cell in the circuit using the pass-transistor logic. Consequently, the optimum driving capability can be obtained and the layout having stable characteristics can be created. In addition, it is possible to ensure the superiority such as a reduction in area, the low consumed power, high-speed operation and the like.
摘要翻译：首先，将给定逻辑电路分为组合电路部分和寄存器部分。通过划分获得的组合电路部分被分成多个具有高连通性的部分电路。每个部分电路被转换成具有晶体管电平的电路。然后，产生具有晶体管电平的部分电路的布局单元。此后，通过使用与组合电路中的每个部分电路中包括的寄存器部分中的每个寄存器对应的布局单元和组合电路中的每个部分电路的布局单元作为单位单元来执行布置和布线，从而创建块布局。因此，具有优异特性的布局可以通过具有CMOS逻辑和传输晶体管逻辑的两个电路中的几种单元产生。特别地，具有高连通性的部分电路使用传输晶体管逻辑布置在电路中的单元中。因此，可以获得最佳的驱动能力，并且可以产生具有稳定特性的布局。另外，可以确保面积减少，低功耗，高速运转等优点。

4. 发明授权

US5986292A Semiconductor integrated logic circuit device 失效
标题翻译：半导体集成逻辑电路器件
公开(公告)号：US5986292A
公开(公告)日：1999-11-16
申请号：US997944
申请日：1997-12-24
申请人： Hiroshi Mizuno , Youichirou Mae , Hidenori Shibata , Kazuo Tsuzuki
发明人： Hiroshi Mizuno , Youichirou Mae , Hidenori Shibata , Kazuo Tsuzuki
IPC分类号： H01L27/02 , H01L27/092 , H01L27/10
CPC分类号： H01L27/092 , H01L27/0207
摘要： An inverter-type basic cell, with a hexagonal contour, comprises one CMOS device pair arrangement including an n-channel transistor and a p-channel transistor. The inverter-type basic cell has a gate region annularly formed and connected in parallel with the n-channel and p-channel transistors, a sectoral drain diffusion region having a vertex at the center of the annularly-formed gate region, and a source diffusion region that is formed outside of the gate region in such a way as to define a shape having two opposing sides that lie on the prolongation of the two radii of the sectoral drain diffusion region.
摘要翻译：具有六边形轮廓的逆变器型基本单元包括包括n沟道晶体管和p沟道晶体管的一个CMOS器件对布置。逆变器型基电池具有环形地形成并与n沟道和p沟道晶体管并联连接的栅极区域，在环状形成的栅极区域的中心具有顶点的扇形漏极扩散区域和源极扩散区域区域，其形成在栅极区域外部，以限定具有位于扇形漏极扩散区域的两个半径的延伸的两个相对侧面的形状。

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