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1. 发明申请

US20120267792A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20120267792A1
公开(公告)日：2012-10-25
申请号：US13455171
申请日：2012-04-25
申请人： Shinichi TAKAYAMA , Kazuo ONO , Tomonori SEKIGUCHI , Akira KOTABE , Yoshimitsu YANAGAWA
发明人： Shinichi TAKAYAMA , Kazuo ONO , Tomonori SEKIGUCHI , Akira KOTABE , Yoshimitsu YANAGAWA
IPC分类号： H01L23/522
CPC分类号： H01L23/5286 , H01L23/481 , H01L25/0657 , H01L2224/16145 , H01L2225/06544
摘要： A stacked device includes a plurality of semiconductor chips connected to each other by through electrodes. The same number of through electrodes are included in each of paths extending from a first power source terminal through each of circuit elements formed for the semiconductor chips to a second power source terminal.
摘要翻译：堆叠式器件包括通过电极彼此连接的多个半导体芯片。在从第一电源端子通过形成为半导体芯片的电路元件的每一个延伸到第二电源端子的每个路径中包括相同数量的贯通电极。

2. 发明申请

US20110176379A1 SEMICONDUCTOR MEMORY DEVICE HAVING MEMORY CELL ARRAY OF OPEN BIT LINE TYPE AND CONTROL METHOD THEREOF 审中-公开
标题翻译：具有开放式线型存储器单元阵列的半导体存储器件及其控制方法
公开(公告)号：US20110176379A1
公开(公告)日：2011-07-21
申请号：US13008408
申请日：2011-01-18
申请人： Shinichi TAKAYAMA , Akira Kotabe , Kazuo Ono , Tomonori Sekiguchi , Yoshimitsu Yanagawa , Riichiro Takemura
发明人： Shinichi TAKAYAMA , Akira Kotabe , Kazuo Ono , Tomonori Sekiguchi , Yoshimitsu Yanagawa , Riichiro Takemura
IPC分类号： G11C7/06
CPC分类号： G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C2207/002
摘要： A semiconductor memory device includes: first and second bit lines of an open bit-line system; a sense amplifier that amplifies a potential difference between the first and second bit lines; a pair of first and second local data lines corresponding to the first and second bit lines, respectively; and a write amplifier circuit. The write amplifier circuit changes a potential of the second local data line without changing a potential of the first local data line at a time of writing data for the first bit line, and changes a potential of the first local data line without changing a potential of the second local data line at a time of writing data for the second bit line.
摘要翻译：半导体存储器件包括：开放位线系统的第一和第二位线; 读出放大器，放大第一和第二位线之间的电位差; 对应于第一和第二位线的一对第一和第二本地数据线; 和写放大器电路。写入放大器电路在写入第一位线的数据时改变第二本地数据线的电位而不改变第一本地数据线的电位，并且在不改变第一本地数据线的电位的情况下改变第一本地数据线的电位在第二位线的数据写入时的第二本地数据线。

3. 发明申请

US20110134678A1 Semiconductor device having hierarchical structured bit line 失效
标题翻译：具有分层结构位线的半导体器件
公开(公告)号：US20110134678A1
公开(公告)日：2011-06-09
申请号：US12926693
申请日：2010-12-03
申请人： Takenori Sato , Kazuhiko Kajigaya , Yoshimitsu Yanagawa , Tomonori Sekiguchi , Akira Kotabe , Satoru Akiyama
发明人： Takenori Sato , Kazuhiko Kajigaya , Yoshimitsu Yanagawa , Tomonori Sekiguchi , Akira Kotabe , Satoru Akiyama
IPC分类号： G11C5/06
CPC分类号： G11C5/06 , G11C7/08 , G11C11/4091 , G11C11/4097 , H01L27/10876 , H01L27/10885
摘要： A sense operation with respect to simultaneously-accessed two memory cells is performed by time division by using two sense amplifiers, and thereafter restore operations are performed simultaneously. With this arrangement, it is not necessary to provide switches in the middle of global bit lines, and no problem occurs when performing the restore operation by time division. Further, because a parasitic CR model of a first sense amplifier and that of a second sense amplifier become mutually the same, high sensitivity can be maintained.
摘要翻译：通过使用两个读出放大器进行时分执行相对于同时访问的两个存储单元的检测操作，然后同时执行恢复操作。通过这种布置，不需要在全局位线的中间设置开关，并且在通过时分执行恢复操作时不会发生问题。此外，由于第一读出放大器和第二读出放大器的寄生CR模型相互相同，因此可以保持高灵敏度。

4. 发明授权

US08872258B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08872258B2
公开(公告)日：2014-10-28
申请号：US13359453
申请日：2012-01-26
申请人： Soichiro Yoshida , Yoshimitsu Yanagawa , Tomonori Sekiguchi , Akira Kotabe
发明人： Soichiro Yoshida , Yoshimitsu Yanagawa , Tomonori Sekiguchi , Akira Kotabe
IPC分类号： H01L29/66
CPC分类号： H01L27/10897 , G11C11/4076 , G11C11/4091 , G11C11/4097 , G11C2207/002 , H01L21/823487 , H01L27/0207
摘要： A semiconductor memory device includes: a sense amplifier; a plurality of memory cell arrays; a shared MOS transistor that connects/disconnects the sense amplifier and a bit line included in the memory cell arrays; and a control circuit that controls operation of the shared MOS transistor. A part or whole of an in-sense-amplifier bit line that is a bit line connecting the sense amplifier and the shared MOS transistor is embedded in a semiconductor substrate.
摘要翻译：半导体存储器件包括：读出放大器; 多个存储单元阵列; 共享MOS晶体管，其连接/断开读出放大器和存储单元阵列中包含的位线; 以及控制所述共享MOS晶体管的动作的控制电路。作为连接读出放大器和共享MOS晶体管的位线的读出放大器位线的一部分或全部嵌入在半导体衬底中。

5. 发明授权

US08860476B2 Semiconductor device using multi-phase clock signal and information processing system including the same 有权
公开(公告)号：US08860476B2
公开(公告)日：2014-10-14
申请号：US14158253
申请日：2014-01-17
申请人： Yoshimitsu Yanagawa , Tomonori Sekiguchi , Akira Kotabe , Takamasa Suzuki
发明人： Yoshimitsu Yanagawa , Tomonori Sekiguchi , Akira Kotabe , Takamasa Suzuki
IPC分类号： H03L7/00 , H03L7/081 , H03K5/159 , H03K5/13 , H03K5/00
CPC分类号： H03L7/00 , H03K5/133 , H03K5/159 , H03K2005/00032 , H03K2005/00052 , H03L7/0816
摘要： Disclosed herein is a device that includes a delay line that includes n delay circuits cascade-connected and delays an input clock signal by k cycles, and a routing circuit that generates multi-phase clock signals having different phases based on at least a part of n output clock signals output from the n delay circuits, respectively. The n and the k are both integers more than 1 and a greatest common divisor thereof is 1.

6. 发明申请

US20130193507A1 SEMICONDUCTOR MEMORY DEVICE 有权
公开(公告)号：US20130193507A1
公开(公告)日：2013-08-01
申请号：US13359453
申请日：2012-01-26
申请人： Soichiro YOSHIDA , Yoshimitsu Yanagawa , Tomonori Sekiguchi , Akira Kotabe
发明人： Soichiro YOSHIDA , Yoshimitsu Yanagawa , Tomonori Sekiguchi , Akira Kotabe
IPC分类号： H01L27/088
CPC分类号： H01L27/10897 , G11C11/4076 , G11C11/4091 , G11C11/4097 , G11C2207/002 , H01L21/823487 , H01L27/0207
摘要： A semiconductor memory device includes: a sense amplifier; a plurality of memory cell arrays; a shared MOS transistor that connects/disconnects the sense amplifier and a bit line included in the memory cell arrays; and a control circuit that controls operation of the shared MOS transistor. A part or whole of an in-sense-amplifier bit line that is a bit line connecting the sense amplifier and the shared MOS transistor is embedded in a semiconductor substrate.

7. 发明申请

US20130057326A1 SEMICONDUCTOR DEVICE USING MULTI-PHASE CLOCK SIGNAL AND INFORMATION PROCESSING SYSTEM INCLUDING THE SAME 有权
标题翻译：使用多相时钟信号的半导体器件和包括其的信息处理系统
公开(公告)号：US20130057326A1
公开(公告)日：2013-03-07
申请号：US13598289
申请日：2012-08-29
申请人： Yoshimitsu YANAGAWA , Tomonori Sekiguchi , Akira Kotabe , Takamasa Suzuki
发明人： Yoshimitsu YANAGAWA , Tomonori Sekiguchi , Akira Kotabe , Takamasa Suzuki
IPC分类号： H03L7/00 , H03H11/26
CPC分类号： H03L7/00 , H03K5/133 , H03K5/159 , H03K2005/00032 , H03K2005/00052 , H03L7/0816
摘要： Disclosed herein is a device that includes a delay line that includes n delay circuits cascade-connected and delays an input clock signal by k cycles, and a routing circuit that generates multi-phase clock signals having different phases based on at least a part of n output clock signals output from the n delay circuits, respectively. The n and the k are both integers more than 1 and a greatest common divisor thereof is 1.
摘要翻译：本文公开了一种包括延迟线的装置，其包括级联的n个延迟电路和将输入时钟信号延迟k个周期的延迟线，以及基于n的至少一部分生成具有不同相位的多相时钟信号的路由电路输出从n个延迟电路输出的时钟信号。 n和k都是大于1的整数，最大公约数为1。

8. 发明授权

US08587117B2 Stacked semiconductor chips having circuit element provided with each of the semiconductor chips 失效
标题翻译：具有设置有每个半导体芯片的电路元件的堆叠半导体芯片
公开(公告)号：US08587117B2
公开(公告)日：2013-11-19
申请号：US13455171
申请日：2012-04-25
申请人： Shinichi Takayama , Kazuo Ono , Tomonori Sekiguchi , Akira Kotabe , Yoshimitsu Yanagawa
发明人： Shinichi Takayama , Kazuo Ono , Tomonori Sekiguchi , Akira Kotabe , Yoshimitsu Yanagawa
IPC分类号： H01L23/34
CPC分类号： H01L23/5286 , H01L23/481 , H01L25/0657 , H01L2224/16145 , H01L2225/06544
摘要： A stacked device includes a plurality of semiconductor chips connected to each other by through electrodes. The same number of through electrodes are included in each of paths extending from a first power source terminal through each of circuit elements formed for the semiconductor chips to a second power source terminal.
摘要翻译：堆叠式器件包括通过电极彼此连接的多个半导体芯片。在从第一电源端子通过形成为半导体芯片的电路元件的每一个延伸到第二电源端子的每个路径中包括相同数量的贯通电极。

9. 发明授权

US09725753B2 Biomolecule information analysis device 有权
公开(公告)号：US09725753B2
公开(公告)日：2017-08-08
申请号：US14122206
申请日：2011-05-31
申请人： Kazuo Ono , Tatsuo Nakagawa , Yoshimitsu Yanagawa , Takayuki Kawahara , Akira Kotabe , Riichiro Takemura
发明人： Kazuo Ono , Tatsuo Nakagawa , Yoshimitsu Yanagawa , Takayuki Kawahara , Akira Kotabe , Riichiro Takemura
IPC分类号： C12Q1/68 , G01N33/487
CPC分类号： C12Q1/68 , C12Q1/6869 , G01N33/48721 , C12Q2565/631
摘要： Provided is a device that, on the basis of a measurement result of a current that has a low value and a wide distribution, identifies the composition of biological molecules passing through a nanoparticle path. This biomolecule information analysis device obtains a current value by applying an electrical field to biomolecules passing through a gap between a first electrode and a second electrode, and identifies the structure of the biomolecules by integrating the current value and making a comparison with a reference value (see FIG. 1).

10. 发明授权

US09144908B2 Manipulator device 有权
标题翻译：机械手装置
公开(公告)号：US09144908B2
公开(公告)日：2015-09-29
申请号：US14114208
申请日：2012-04-18
申请人： Makoto Saen , Kiyoto Ito , Yoshimitsu Yanagawa , Tomomi Takahashi
发明人： Makoto Saen , Kiyoto Ito , Yoshimitsu Yanagawa , Tomomi Takahashi
IPC分类号： B25J15/00 , B25J19/00 , B25J15/08 , B25J15/02 , B25J13/08 , G01L5/22 , B25J9/16 , G01L5/00
CPC分类号： B25J15/0253 , B25J9/1612 , B25J13/083 , B25J13/085 , G01L5/009 , G01L5/228 , Y10S901/32 , Y10S901/34 , Y10S901/47
摘要： A manipulator device has an arm portion and a hand portion The hand portion includes one or more finger portions that manipulate a target object. Each finger portion includes a slip sensor and multiple contact sensors, with at least one contact sensor at a position proximate to the slip sensor and at least another contact sensor at a position remote from the slip sensor. When the contact sensors at the positions remote from the slip sensor detect contact of the target object and the contact sensors arranged at the positions proximate to the slip sensors do not detect contact, a position of the finger portion is moved by a distance corresponding to the distance between the contact sensors detecting contact of the target object and the contact sensors arranged at the positions proximate to the slip such that a detecting position of the slip sensor is coincident with a position of the target object.
摘要翻译：操纵器装置具有臂部和手部。手部包括操纵目标物体的一个或多个手指部。每个手指部分包括滑动传感器和多个接触传感器，其中至少一个接触传感器位于靠近滑动传感器的位置处，并且至少另一个接触传感器位于远离滑移传感器的位置。当远离滑动传感器的位置处的接触传感器检测到目标物体的接触点和布置在靠近滑动传感器的位置处的接触传感器没有检测到接触时，手指部分的位置移动相应于接触传感器之间的距离检测目标物体的接触点和布置在接近滑动位置的接触传感器之间的距离，使得滑动传感器的检测位置与目标物体的位置一致。

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