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1. 发明授权

US07674634B2 Method of producing semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US07674634B2
公开(公告)日：2010-03-09
申请号：US10532249
申请日：2003-11-05
申请人： Kenji Maruyama , Masaki Kurasawa , Masao Kondo , Yoshihiro Arimoto
发明人： Kenji Maruyama , Masaki Kurasawa , Masao Kondo , Yoshihiro Arimoto
IPC分类号： H01L21/8246
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55
摘要： A semiconductor device incorporating a capacitor structure that includes a ferroelectric thin film is obtained by forming, on a single crystalline substrate 10 having a surface suited for growing thereon a thin film layer of ferroelectric single crystal having a plane (111), a ferroelectric single crystalline thin film 12′ containing Pb and having a plane (111) 11 in parallel with the surface of the substrate (or a ferroelectric polycrystalline thin film containing Pb and oriented parallel with the plane (111) in parallel with the surface of the substrate) and part 16 of a circuit of a semiconductor device, to thereby fabricate the single crystalline substrate 10 having said ferroelectric thin film containing Pb and said part of the circuit of the semiconductor device; and bonding said single crystalline substrate 10 to another substrate on which the other circuit of the semiconductor device has been formed in advance, to couple the two circuits together.The capacitor in the semiconductor device thus obtained includes a ferroelectric thin film having a large amount of polarizing charge. The semiconductor device can be used as a highly reliable nonvolatile memory.
摘要翻译：通过在具有适于生长表面的单晶衬底10上形成具有平面（111）的铁电单晶薄膜层，铁电单结晶含有Pb的具有与基板表面平行的平面（111）11的薄膜12'（或含有Pb的铁电体多晶薄膜，与基板的表面平行取向平行），以及半导体器件的电路的第16部分，从而制造具有含有Pb的所述铁电薄膜和所述半导体器件的所述电路的所述部分的单晶衬底10; 并将所述单晶衬底10预先连接到其上形成有半导体器件的另一电路的另一衬底上，以将两个电路耦合在一起。由此得到的半导体装置中的电容器具有大量的极化电荷的铁电薄膜。半导体器件可以用作高度可靠的非易失性存储器。

2. 发明授权

US6159858A Slurry containing manganese oxide and a fabrication process of a semiconductor device using such a slurry 失效
标题翻译：含有锰氧化物的浆料和使用这种浆料的半导体器件的制造方法
公开(公告)号：US6159858A
公开(公告)日：2000-12-12
申请号：US884165
申请日：1997-06-27
申请人： Sadahiro Kishii , Ko Nakamura , Yoshihiro Arimoto , Akiyoshi Hatada , Rintaro Suzuki , Naruo Ueda , Kenzo Hanawa
发明人： Sadahiro Kishii , Ko Nakamura , Yoshihiro Arimoto , Akiyoshi Hatada , Rintaro Suzuki , Naruo Ueda , Kenzo Hanawa
IPC分类号： C03C19/00 , C09G1/02 , C09K3/14 , C09K13/04 , H01L21/02 , H01L21/306 , H01L21/3105 , H01L21/321 , H01L21/302
CPC分类号： C09G1/02 , C03C19/00 , C09K3/1409 , C09K3/1463 , C09K3/1472 , C09K13/04 , H01L21/02065 , H01L21/02074 , H01L21/31053 , H01L21/3212
摘要： A slurry contains MnO.sub.2 or other manganese oxide as a primary component of abrasive particles. Further, a polishing process using such a manganese oxide abrasive and a fabrication process of a semiconductor device using such a polishing process are disclosed.
摘要翻译：浆料含有MnO 2或其它氧化锰作为磨料颗粒的主要成分。此外，公开了使用这种氧化锰研磨剂的研磨工艺和使用这种抛光工艺的半导体器件的制造工艺。

3. 发明授权

US5877089A Slurry containing manganese oxide 失效
标题翻译：含有氧化锰的浆料
公开(公告)号：US5877089A
公开(公告)日：1999-03-02
申请号：US14246
申请日：1998-01-27
申请人： Sadahiro Kishii , Akiyoshi Hatada , Rintaro Suzuki , Hiroshi Horie , Yoshihiro Arimoto , Ko Nakamura
发明人： Sadahiro Kishii , Akiyoshi Hatada , Rintaro Suzuki , Hiroshi Horie , Yoshihiro Arimoto , Ko Nakamura
IPC分类号： C09G1/02 , C09K3/14 , H01L21/3105 , H01L21/463
CPC分类号： H01L21/31053 , C09G1/02 , C09K3/1463 , H01L21/463
摘要： A slurry contains MnO.sub.2 or other manganese oxide as a primary component of abrasive particles. Further, a polishing process using such a manganese oxide abrasive and a fabrication process of a semiconductor device using such a polishing process are disclosed.
摘要翻译：浆料含有MnO 2或其它氧化锰作为磨料颗粒的主要成分。此外，公开了使用这种氧化锰研磨剂的研磨工艺和使用这种抛光工艺的半导体器件的制造工艺。

4. 发明授权

US5763325A Fabrication process of a semiconductor device using a slurry containing manganese oxide 失效
标题翻译：使用含有氧化锰的浆料的半导体器件的制造方法
公开(公告)号：US5763325A
公开(公告)日：1998-06-09
申请号：US674507
申请日：1996-07-02
申请人： Sadahiro Kishii , Akiyoshi Hatada , Rintaro Suzuki , Hiroshi Horie , Yoshihiro Arimoto , Ko Nakamura
发明人： Sadahiro Kishii , Akiyoshi Hatada , Rintaro Suzuki , Hiroshi Horie , Yoshihiro Arimoto , Ko Nakamura
IPC分类号： C09G1/02 , C09K3/14 , H01L21/3105 , H01L21/463
CPC分类号： H01L21/31053 , C09G1/02 , C09K3/1463 , H01L21/463
摘要： A slurry contains MnO.sub.2 or other manganese oxide as a primary component of abrasive particles. Further, a polishing process using such a manganese oxide abrasive and a fabrication process of a semiconductor device using such a polishing process are disclosed.
摘要翻译：浆料含有MnO 2或其它氧化锰作为磨料颗粒的主要成分。此外，公开了使用这种氧化锰研磨剂的研磨工艺和使用这种抛光工艺的半导体器件的制造工艺。

5. 发明申请

US20060166378A1 Method of producing semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US20060166378A1
公开(公告)日：2006-07-27
申请号：US10532249
申请日：2003-11-05
申请人： Kenji Maruyama , Masaki Kurasawa , Masao Kondo , Yoshihiro Arimoto
发明人： Kenji Maruyama , Masaki Kurasawa , Masao Kondo , Yoshihiro Arimoto
IPC分类号： H01L21/20 , H01L21/00
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55
摘要： A semiconductor device incorporating a capacitor structure that includes a ferroelectric thin film is obtained by forming, on a single crystalline substrate 10 having a surface suited for growing thereon a thin film layer of ferroelectric single crystal having a plane (111), a ferroelectric single crystalline thin film 12′ containing Pb and having a plane (111) 11 in parallel with the surface of the substrate (or a ferroelectric polycrystalline thin film containing Pb and oriented parallel with the plane (111) in parallel with the surface of the substrate) and part 16 of a circuit of a semiconductor device, to thereby fabricate the single crystalline substrate 10 having said ferroelectric thin film containing Pb and said part of the circuit of the semiconductor device; and bonding said single crystalline substrate 10 to another substrate on which the other circuit of the semiconductor device has been formed in advance, to couple the two circuits together. The capacitor in the semiconductor device thus obtained includes a ferroelectric thin film having a large amount of polarizing charge. The semiconductor device can be used as a highly reliable nonvolatile memory.
摘要翻译：通过在具有适于生长表面的单晶衬底10上形成具有平面（111）的铁电单晶薄膜层，铁电单结晶含有Pb的具有与基板表面平行的平面（111）11的薄膜12'（或含有Pb的铁电体多晶薄膜，与基板的表面平行取向平行），以及半导体器件的电路的第16部分，从而制造具有含有Pb的所述铁电薄膜和所述半导体器件的所述电路的所述部分的单晶衬底10; 并将所述单晶衬底10预先连接到其上形成有半导体器件的另一电路的另一衬底上，以将两个电路耦合在一起。由此得到的半导体装置中的电容器具有极性电荷量大的铁电薄膜。半导体器件可以用作高度可靠的非易失性存储器。

6. 发明授权

US5760343A Combinational weighing systems and methods for automatically aligning weighed article batches 失效
标题翻译：组合称重系统和自动对准称重物料批次的方法
公开(公告)号：US5760343A
公开(公告)日：1998-06-02
申请号：US880241
申请日：1997-06-23
申请人： Yoshihiro Arimoto , Kenzo Tsuzuike , Michihiko Yonetsu , Yoshiharu Asai
发明人： Yoshihiro Arimoto , Kenzo Tsuzuike , Michihiko Yonetsu , Yoshiharu Asai
IPC分类号： G01G19/393 , G01G19/42 , G01G13/00
CPC分类号： G01G19/393 , G01G19/42 , B65G2201/0205
摘要： A combinational weighing system receives articles sequentially in a plurality of mutually parallel supply lines to be sequentially transported to weighing devices which are individually associated therewith and weigh batches of the articles received therefrom. Combinations of the measured weight values are combined and a particular combination of article batches is selected as having a total weight which satisfies a predefined condition. The article batches in the selected combination are transported in a general direction of flow from the weighing devices to an outlet in mutually different travel modes such that they are automatically aligned one behind another in the direction of flow as they are discharged together through the outlet.
摘要翻译：组合称重系统在多个相互平行的供应管线中顺序地接收物品，以顺序地运送到与其单独关联的称重设备并且对从其接收的物品的批量进行称重。将所测量的重量值的组合组合，并且将物品批次的特定组合选择为具有满足预定条件的总重量。所选择的组合中的物品批量在大体上从称重装置的方向传送到相互不同的行进模式的出口，使得当它们通过出口一起排放时，它们在流动方向上自动对准。

7. 发明授权

US5562529A Apparatus and method for uniformly polishing a wafer 失效
标题翻译：用于均匀抛光晶片的装置和方法
公开(公告)号：US5562529A
公开(公告)日：1996-10-08
申请号：US131949
申请日：1993-10-08
申请人： Sadahiro Kishii , Yoshihiro Arimoto , Hiroshi Horie , Fumitoshi Sugimoto
发明人： Sadahiro Kishii , Yoshihiro Arimoto , Hiroshi Horie , Fumitoshi Sugimoto
IPC分类号： B24B37/013 , B24B49/10 , B24B1/00 , B24B7/16
CPC分类号： B24B37/013 , B24B49/10 , Y10S451/908
摘要： An apparatus and method for polishing a semiconductor wafer. A polisher includes a supporting plate having a conductive film and a polishing cloth formed on the conductive film of the supporting plate. The polishing cloth has a plurality of openings to expose the conductive film. A wafer holder has a conductive wafer holding surface to hold a semiconductor wafer having current detective patterns and an insulating film covering the current detective patterns. A polishing slurry supply device supplies a polishing slurry including ions to either the polishing cloth or the semiconductor wafer. A current detecting device, connected to the supporting plate and the wafer holder, detects a magnitude of a current flowing across the supporting plate and the wafer holder through the conductive wafer holding surface, the semiconductor wafer held by the wafer holder, the current detective patterns of the semiconductor wafer, the polishing slurry filled in the openings of the polishing cloth, and the conductive film.
摘要翻译：一种用于抛光半导体晶片的装置和方法。抛光机包括具有导电膜的支撑板和形成在支撑板的导电膜上的抛光布。抛光布具有多个开口以露出导电膜。晶片保持器具有导电晶片保持表面，以保持具有电流检测图案的半导体晶片和覆盖当前检测图案的绝缘膜。研磨浆料供给装置将包含离子的研磨浆料供给到研磨布或半导体晶片。连接到支撑板和晶片保持器的电流检测装置检测通过导电晶片保持表面流过支撑板和晶片保持器的电流的大小，由晶片保持器保持的半导体晶片，当前的检测模式的半导体晶片，填充在抛光布的开口中的抛光浆料和导电膜。

8. 发明授权

US5399233A Method of and apparatus for manufacturing a semiconductor substrate 失效
标题翻译：用于制造半导体衬底的方法和装置
公开(公告)号：US5399233A
公开(公告)日：1995-03-21
申请号：US969290
申请日：1993-02-01
申请人： Maki Murazumi , Yoshihiro Arimoto , Atsushi Fukuroda
发明人： Maki Murazumi , Yoshihiro Arimoto , Atsushi Fukuroda
IPC分类号： H01L21/304 , H01L21/306 , H01L21/762 , H01L27/12
CPC分类号： H01L21/30625 , H01L21/76251 , Y10S438/959 , Y10S438/977
摘要： In a process of manufacturing a semiconductor substrate having a SOI (silicon on insulator) structure, grooves are formed in a silicon layer reduced in thickness to several microns so that the silicon layer is separated into island-like regions corresponding to a chip size or device regions, and a stopper having a thickness corresponding to a desired final thickness of the silicon layer is formed in the grooves. The silicon layer is scanned with a piece of polishing cloth which has an area larger than that of each island-like region but sufficiently smaller than that of silicon layer and which is attached to a pressing surface of the polishing jig, thereby polishing the silicon layer until the stopper is exposed. The thickness of the silicon layer is measured at a position such that the thickness of a portion thereof is measured immediately before the same portion is polished. The pressure applied to the polishing cloth or the rotational speed of the polishing jig is controlled on the basis of thickness data thereby obtained. The thickness of a silicon layer having a diameter of 6 inches was thereby reduced uniformly to 0.1 to 1 .mu.m.
摘要翻译： PCT No.PCT / JP92 / 01586 Sec。 371日期：1993年2月1日在制造具有SOI（绝缘体上硅）结构的半导体衬底的工艺中，在厚度减小到几微米的硅层中形成凹槽，因此，硅层被分离成对应于芯片尺寸或器件区域的岛状区域，并且在沟槽中形成具有对应于硅层的期望最终厚度的厚度的塞子。用一块抛光布扫描硅层，该抛光布的面积大于每个岛状区域的面积，但比硅层的面积大得多，并附着在抛光夹具的压制表面上，从而抛光硅层直到塞子被暴露。测量硅层的厚度，使其一部分的厚度在相同部分被抛光之前立即测量。基于由此获得的厚度数据来控制施加到抛光布上的压力或抛光夹具的转速。因此，直径为6英寸的硅层的厚度均匀地降低至0.1至1μm。

9. 发明授权

US5413951A Composite semiconductor substrate and a fabrication process thereof 失效
标题翻译：复合半导体衬底及其制造工艺
公开(公告)号：US5413951A
公开(公告)日：1995-05-09
申请号：US19888
申请日：1993-02-19
申请人： Tatsuya Ohori , Isamu Hanyu , Fumitoshi Sugimoto , Yoshihiro Arimoto
发明人： Tatsuya Ohori , Isamu Hanyu , Fumitoshi Sugimoto , Yoshihiro Arimoto
IPC分类号： H01L27/12 , H01L21/02 , H01L21/20 , H01L27/01 , H01L29/04 , H01L21/302
CPC分类号： H01L21/76256 , H01L21/2007 , Y10S148/135
摘要： A method for fabricating an SOI structure which includes the steps of contacting a single crystal layer of a group III-V compound semiconductor material to a single crystal substrate of sapphire such that a principal surface of said single crystal layer establishes an intimate contact with a corresponding principal surface of said single crystal substrate and bonding the single crystal layer and the single crystal substrate with each other while elevating a temperature.
摘要翻译：一种制造SOI结构的方法，其包括将III-V族化合物半导体材料的单晶层与蓝宝石的单晶衬底接触的步骤，使得所述单晶层的主表面与相应的所述单晶基板的主表面，并且在升高温度的同时将单晶层和单晶基板彼此接合。

10. 发明授权

US07465980B2 Ferroelectric memory, multivalent data recording method and multivalent data reading method 有权
标题翻译：铁电存储器，多值数据记录方法和多值数据读取方法
公开(公告)号：US07465980B2
公开(公告)日：2008-12-16
申请号：US11220902
申请日：2005-09-08
申请人： Yoshihiro Arimoto , Hiroshi Ishihara , Tetsuro Tamura , Hiromasa Hoko , Koji Aizawa , Yoshiaki Tabuchi , Masaomi Yamaguchi , Yasuo Nara , Kazuhiro Takahashi , Satoshi Hasegawa
发明人： Yoshihiro Arimoto , Hiroshi Ishihara , Tetsuro Tamura , Hiromasa Hoko , Koji Aizawa , Yoshiaki Tabuchi , Masaomi Yamaguchi , Yasuo Nara , Kazuhiro Takahashi , Satoshi Hasegawa
IPC分类号： H01L29/76
CPC分类号： G11C11/22 , G11C11/5657 , H01L21/28291 , H01L29/6684 , H01L29/78391
摘要： A ferroelectric memory device includes a gate electrode formed on a semiconductor body via a ferroelectric film, first and second diffusion regions being formed in the semiconductor body at respective sides of a channel region, wherein the ferroelectric film comprises a first region located in the vicinity of the first diffusion region, a second region located in the vicinity of the second diffusion region, and a third region located between the first and second regions, wherein the first, second and third regions carry respective, mutually independent polarizations.
摘要翻译：铁电存储器件包括通过铁电体膜形成在半导体本体上的栅电极，第一和第二扩散区域形成在沟道区域的各个侧面的半导体本体中，其中铁电体膜包括位于第一区域附近的第一区域所述第一扩散区域，位于所述第二扩散区域附近的第二区域和位于所述第一和第二区域之间的第三区域，其中所述第一区域，第二区域和第三区域携带各自相互独立的极化。

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