专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20140374840A1 SEMICONDUCTOR DEVICES USING MOS TRANSISTORS WITH NONUNIFORM GATE ELECTRODE STRUCTURES AND METHODS OF FABRICATING THE SAME 审中-公开
标题翻译：使用具有非共振栅极电极结构的MOS晶体管的半导体器件及其制造方法
公开(公告)号：US20140374840A1
公开(公告)日：2014-12-25
申请号：US14312109
申请日：2014-06-23
申请人： Hye-Lan Lee , Sang-Bom Kang , Jae-Jung Kim , Moon-Kyu Park , Jae-Yeol Song , June-Hee Lee , Yong-Ho Ha , Sang-Jin Hyun
发明人： Hye-Lan Lee , Sang-Bom Kang , Jae-Jung Kim , Moon-Kyu Park , Jae-Yeol Song , June-Hee Lee , Yong-Ho Ha , Sang-Jin Hyun
IPC分类号： H01L27/088
CPC分类号： H01L27/0886 , H01L21/823821 , H01L21/823842 , H01L21/82385 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/165 , H01L29/4966 , H01L29/517 , H01L29/66545
摘要： A semiconductor device includes a substrate and first and second gate electrodes on the substrate. The first gate electrode includes a first gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion and away from the substrate defining a first trench having a first width and a first functional film filling the first trench. The second gate electrode includes a second gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion defining a second trench having a second width different from the first width, a second functional film conforming to the second gate insulation film in the second trench and defining a third trench, and a metal region in the third trench. The first width may be less than the second width.
摘要翻译：半导体器件包括衬底和衬底上的第一和第二栅电极。第一栅极电极包括第一栅极绝缘膜，该第一栅极绝缘膜具有在基板上的底部部分以及侧壁部分，其从底部延伸并远离基板限定具有第一宽度的第一沟槽和填充第一沟槽的第一功能膜。所述第二栅电极包括第二栅极绝缘膜，所述第二栅极绝缘膜具有在所述基板上的底部部分和从所述底部部分延伸的侧壁部分，所述侧壁部分限定具有不同于所述第一宽度的第二宽度的第二沟槽;第二功能膜，在第二沟槽中并且限定第三沟槽，以及第三沟槽中的金属区域。第一宽度可以小于第二宽度。

2. 发明授权

US08445354B2 Methods for manufacturing a phase-change memory device 有权
标题翻译：相变存储器件的制造方法
公开(公告)号：US08445354B2
公开(公告)日：2013-05-21
申请号：US13368852
申请日：2012-02-08
申请人： Yong-Ho Ha , Bong-Jin Kuh , Han-Bong Ko , Doo-Hwan Park , Sang-Wook Lim , Hee-Ju Shin
发明人： Yong-Ho Ha , Bong-Jin Kuh , Han-Bong Ko , Doo-Hwan Park , Sang-Wook Lim , Hee-Ju Shin
IPC分类号： H01L21/20
CPC分类号： H01L45/06 , C04B35/56 , C04B35/573 , C04B2235/3817 , C04B2235/3839 , C04B2235/3843 , C04B2235/40 , C04B2235/402 , C04B2235/404 , C04B2235/405 , C04B2235/408 , C04B2235/428 , G11C13/0004 , H01L27/2436 , H01L45/1233 , H01L45/144 , H01L45/1625 , H01L45/1675 , H01L45/1683
摘要： A method of manufacturing a phase-change memory device comprises forming a contact region on a substrate, forming a lower electrode electrically connected to the contact region, forming a phase-change material layer on the lower electrode using a chalcogenide compound target including carbon and metal, or carbon, nitrogen and metal, and forming an upper electrode on the phase-change material layer.
摘要翻译：一种相变存储器件的制造方法，包括：在基板上形成接触区域，形成与所述接触区域电连接的下部电极，使用包含碳和金属的硫属化物化合物靶，在所述下部电极上形成相变材料层，或碳，氮和金属，并且在相变材料层上形成上电极。

3. 发明授权

US08012789B2 Nonvolatile memory device and method of manufacturing the same 失效
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US08012789B2
公开(公告)日：2011-09-06
申请号：US12379277
申请日：2009-02-18
申请人： Han-Bong Ko , Yong-Ho Ha , Doo-Hwan Park , Bong-Jin Kuh , Hee-Ju Shin
发明人： Han-Bong Ko , Yong-Ho Ha , Doo-Hwan Park , Bong-Jin Kuh , Hee-Ju Shin
IPC分类号： H01L21/00
CPC分类号： H01L45/143 , G11C13/0004 , G11C2213/51 , G11C2213/72 , G11C2213/79 , H01L27/2409 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/12 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16 , H01L45/1675
摘要： A nonvolatile memory device, including a lower electrode on a semiconductor substrate, a phase change material pattern on the lower electrode, an adhesion pattern on the phase change material pattern and an upper electrode on the adhesion pattern, wherein the adhesion pattern includes a conductor including nitrogen.
摘要翻译：一种非易失性存储器件，包括半导体衬底上的下电极，下电极上的相变材料图案，相变材料图案上的粘合图案和粘附图案上的上电极，其中粘附图案包括：导体，包括氮。

4. 发明申请

US20100019216A1 MULTI-LAYER PHASE-CHANGEABLE MEMORY DEVICES 有权
标题翻译：多层相变存储器件
公开(公告)号：US20100019216A1
公开(公告)日：2010-01-28
申请号：US12568402
申请日：2009-09-28
申请人： Jeong-Hee Park , Ju-Chul Park , Jun-Soo Bae , Bong-Jin Kuh , Yong-Ho Ha
发明人： Jeong-Hee Park , Ju-Chul Park , Jun-Soo Bae , Bong-Jin Kuh , Yong-Ho Ha
IPC分类号： H01L47/00
CPC分类号： H01L45/06 , G11C13/0004 , G11C2213/79 , H01L45/1233 , H01L45/143 , H01L45/144 , H01L45/1625 , H01L45/1675
摘要： A phase-changeable memory device includes a phase-changeable material pattern and first and second electrodes electrically connected to the phase-changeable material pattern. The first and second electrodes are configured to provide an electrical signal to the phase-changeable material pattern. The phase-changeable material pattern includes a first phase-changeable material layer and a second phase-changeable material layer. The first and second phase-changeable material patterns have different chemical, physical, and/or electrical characteristics. For example, the second phase-changeable material layer may have a greater resistivity than the first phase-changeable material layer. For instance, the first phase-changeable material layer may include nitrogen at a first concentration, and the second phase-changeable material layer may include nitrogen at a second concentration that is greater than the first concentration. Related devices and fabrication methods are also discussed.
摘要翻译：可变相存储器件包括相变材料图案，以及电连接到相变材料图案的第一和第二电极。第一和第二电极被配置为向相变材料图案提供电信号。相变材料图案包括第一相变材料层和第二相变材料层。第一和第二可相变材料图案具有不同的化学，物理和/或电特性。例如，第二相变材料层可以具有比第一相变材料层更大的电阻率。例如，第一相变材料层可以包括第一浓度的氮，第二相变材料层可以包括大于第一浓度的第二浓度的氮。还讨论了相关设备和制造方法。

5. 发明授权

US07495456B2 System and method of determining pulse properties of semiconductor device 有权
标题翻译：确定半导体器件的脉冲特性的系统和方法
公开(公告)号：US07495456B2
公开(公告)日：2009-02-24
申请号：US11361412
申请日：2006-02-24
申请人： Hideki Horii , Yong-Ho Ha
发明人： Hideki Horii , Yong-Ho Ha
IPC分类号： G01R27/08
CPC分类号： G01R31/2601
摘要： Provided are a system and method of determining pulse properties of a semiconductor device. An embodiment of the system includes at least one pair of first and second probes electrically contacting terminals of the semiconductor resistance device, a pulse generator connected to the first probe and outputting pulse signals, an oscilloscope having at least one pair of first and second channels, wherein the pulse electric signal is supplied to the first channel and the first probe and the second channel is connected to the second probe. The oscilloscope calculates a pulse current flowing in terminals of the semiconductor resistance device using the second channel and determines a dynamic resistance of the semiconductor resistance device using the first and second channels.
摘要翻译：提供一种确定半导体器件的脉冲特性的系统和方法。该系统的一个实施例包括至少一对电接触半导体电阻器件的端子的第一和第二探针，连接到第一探针并输出脉冲信号的脉冲发生器，具有至少一对第一和第二通道的示波器，其中所述脉冲电信号被提供给所述第一通道，并且所述第一探针和所述第二通道连接到所述第二探针。示波器使用第二通道计算在半导体电阻器件的端子中流动的脉冲电流，并且使用第一和第二通道确定半导体电阻器件的动态电阻。

6. 发明申请

US20080073637A1 Phase-Change Material Layer and Phase-Change Memory Device Including the Phase-Change Material Layer 有权
标题翻译：相变材料层和包括相变材料层的相变存储器件
公开(公告)号：US20080073637A1
公开(公告)日：2008-03-27
申请号：US11860975
申请日：2007-09-25
申请人： Bong-Jin Kuh , Yong-Ho Ha , Han-Bong Ko , Doo-Hwan Park , Hee-Ju Shin , Sang-Wook Lim
发明人： Bong-Jin Kuh , Yong-Ho Ha , Han-Bong Ko , Doo-Hwan Park , Hee-Ju Shin , Sang-Wook Lim
IPC分类号： H01L47/00 , C09K3/00
CPC分类号： H01L45/1233 , H01L27/2409 , H01L27/2436 , H01L45/06 , H01L45/143 , H01L45/144 , H01L45/1616 , H01L45/1625 , H01L45/1675 , H01L45/1683
摘要： A phase-change memory device includes a substrate having a contact region, an insulating interlayer on the substrate, a lower electrode electrically connected to the contact region, a phase-change material layer pattern formed on the lower electrode, and an upper electrode formed on the phase-change material layer pattern. The phase-change material layer pattern includes a chalcogenide compound doped with carbon and at least one of nitrogen and metal. The phase-change memory device may have a considerably reduced driving current without increasing a set resistance thereof. Further, the phase-change material layer pattern may have an increased crystallization temperature so as to ensure improved data retention characteristics of the phase-change memory device.
摘要翻译：相变存储器件包括：具有接触区域的基板，基板上的绝缘中间层，与接触区域电连接的下部电极;形成在下部电极上的相变材料层图案;以及上部电极，相变材料层图案。相变材料层图案包括掺杂有碳和氮和金属中的至少一种的硫族化合物。相变存储器件可以具有显着降低的驱动电流，而不增加其设定电阻。此外，相变材料层图案可以具有增加的结晶温度，以确保相变存储器件的数据保持特性的改善。

7. 发明申请

US20070267721A1 Phase Change Memory Cell Employing a GeBiTe Layer as a Phase Change Material Layer, Phase Change Memory Device Including the Same, Electronic System Including the Same and Method of Fabricating the Same 有权
标题翻译：使用GeBiTe层作为相变材料层的相变存储单元，包括其的相变存储器件，包括其的电子系统及其制造方法
公开(公告)号：US20070267721A1
公开(公告)日：2007-11-22
申请号：US11747395
申请日：2007-05-11
申请人： Bong-Jin Kuh , Yong-Ho Ha , Doo-Hwan Park , Jeong-Hee Park , Han-Bong Ko
发明人： Bong-Jin Kuh , Yong-Ho Ha , Doo-Hwan Park , Jeong-Hee Park , Han-Bong Ko
IPC分类号： H01L31/117 , H01L29/12
CPC分类号： H01L45/144 , G11C11/5678 , G11C13/0004 , G11C2213/72 , G11C2213/79 , H01L27/2409 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/1625
摘要： A phase change memory cell includes an interlayer insulating layer formed on a semiconductor substrate, and a first electrode and a second electrode disposed in the interlayer insulating layer. A phase change material layer is disposed between the first and second electrodes. The phase change material layer may be an undoped GeBiTe layer, a doped GeBiTe layer containing an impurity or a doped GeTe layer containing an impurity. The undoped GeBiTe layer has a composition ratio within a range surrounded by four points (A1(Ge21.43, Bi16.67, Te61.9), A2(Ge44.51, Bi0.35, Te55.14), A3(Ge59.33, Bi0.5, Te40.17) and A4(Ge38.71, Bi16.13, Te45.16)) represented by coordinates on a triangular composition diagram having vertices of germanium (Ge), bismuth (Bi) and tellurium (Te). The doped GeBiTe layer contains an impurity and has a composition ratio within a range surrounded by four points (D1(Ge10, Bi20, Te70), D2(Ge30, Bi0, Te70), D3(Ge70, Bi0, Te30) and D4(Ge50, Bi20, Te30)) represented by coordinates on the triangular composition diagram.
摘要翻译：相变存储单元包括形成在半导体衬底上的层间绝缘层和设置在层间绝缘层中的第一电极和第二电极。相变材料层设置在第一和第二电极之间。相变材料层可以是未掺杂的GeBiTe层，包含杂质的掺杂GeBiTe层或含有杂质的掺杂GeTe层。未掺杂的GeBiTe层的组成比在四个点（A 1（Ge 21.43，Bi 16.67，Te 61.9）， A 2（Ge 44.51，Bi 0.35，Te 55.14），A 3（Ge 59.33，Bi _{40 ，Te <40.17 和A 4（Ge 38.71，Bi 16.13，Te 45.16）））由具有锗（Ge），铋（Bi）和碲（Te）的顶点的三角形组成图上的坐标表示。掺杂的GeBiTe层含有杂质，其组成比在四个点（D 1（Ge 10 O 12，Bi 20 O，Te 70）（3），D 2（Ge 30 30，Bi 0，Te 70），D 3（Ge 70），Bi 2 O 3，Te 30 N）和D 4（Ge 50，Bi 20，Te 30 ））由三角形组成图上的坐标表示。}

8. 发明授权

US07126846B2 Method and driver for programming phase change memory cell 失效
公开(公告)号：US07126846B2
公开(公告)日：2006-10-24
申请号：US11401861
申请日：2006-04-12
申请人： Yong-ho Ha , Beak-hyung Cho , Ji-hye Yi
发明人： Yong-ho Ha , Beak-hyung Cho , Ji-hye Yi
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C7/04 , G11C13/0004 , G11C2013/0092
摘要： In the method of programming a phase change memory cell, having a lower resistive state and a higher resistive state, to the lower resistive state, the memory cell is heated to first temperature. Subsequently, the memory cell is heated to second temperature, which is greater than the first temperature.

9. 发明申请

US20060181931A1 METHOD AND DRIVER FOR PROGRAMMING PHASE CHANGE MEMORY CELL 失效
标题翻译：编程相变记忆细胞的方法与驱动
公开(公告)号：US20060181931A1
公开(公告)日：2006-08-17
申请号：US11401866
申请日：2006-04-12
申请人： Yong-ho Ha , Beak-hyung Cho , Ji-hye Yi
发明人： Yong-ho Ha , Beak-hyung Cho , Ji-hye Yi
IPC分类号： G11C16/06
CPC分类号： G11C13/0069 , G11C7/04 , G11C13/0004 , G11C2013/0092
摘要： In the method of programming a phase change memory cell, having a lower resistive state and a higher resistive state, to the lower resistive state, the memory cell is heated to first temperature. Subsequently, the memory cell is heated to second temperature, which is greater than the first temperature.
摘要翻译：在将具有较低电阻状态和较高电阻状态的相变存储单元编程为较低电阻状态的方法中，将存储单元加热至第一温度。随后，将存储单元加热至大于第一温度的第二温度。

10. 发明申请

US20060016396A1 Apparatus for depositing a thin film on a substrate 审中-公开
标题翻译：用于在基板上沉积薄膜的装置
公开(公告)号：US20060016396A1
公开(公告)日：2006-01-26
申请号：US11179136
申请日：2005-07-12
申请人： Bong-Jin Kuh , Horii Hideki , Soon-Oh Park , Jang-Eun Lee , Yong-Ho Ha
发明人： Bong-Jin Kuh , Horii Hideki , Soon-Oh Park , Jang-Eun Lee , Yong-Ho Ha
IPC分类号： C23C16/00
CPC分类号： C23C14/165 , C23C14/046 , C23C14/35 , C23C14/50
摘要： An apparatus for depositing a thin film on a substrate includes a housing, a substrate support portion, a securing member, a heater, a target member and a plasma generator. The housing defines a process chamber. The substrate support portion is disposed in the process chamber to support the substrate. The securing member is adapted to non-electrically secure the substrate to the substrate support portion during performance of a process. The heater is provided to maintain the substrate supported by the substrate support portion at a process temperature. The target member faces the substrate support portion and includes materials to be deposited on the substrate. The plasma generator is adapted to excite a process gas supplied into the process chamber into a plasma state.
摘要翻译：用于在衬底上沉积薄膜的装置包括壳体，衬底支撑部分，固定构件，加热器，目标构件和等离子体发生器。壳体限定了处理室。衬底支撑部分设置在处理室中以支撑衬底。固定构件适于在执行过程期间将基板非电气地固定到基板支撑部分。提供加热器以将基板支撑部分支撑的基板保持在处理温度。目标构件面向衬底支撑部分并且包括待沉积在衬底上的材料。等离子体发生器适于将供应到处理室中的工艺气体激发成等离子体状态。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式