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1. 发明授权

US08836038B2 CMOS dual metal gate semiconductor device 有权
标题翻译： CMOS双金属栅极半导体器件
公开(公告)号：US08836038B2
公开(公告)日：2014-09-16
申请号：US12883241
申请日：2010-09-16
申请人： Yong-Tian Hou , Peng-Fu Hsu , Jin Ying , Kang-Cheng Lin , Kuo-Tai Huang , Tze-Liang Lee
发明人： Yong-Tian Hou , Peng-Fu Hsu , Jin Ying , Kang-Cheng Lin , Kuo-Tai Huang , Tze-Liang Lee
IPC分类号： H01L29/78 , H01L21/8238 , H01L21/28 , H01L29/66
CPC分类号： H01L21/823842 , H01L21/28044 , H01L21/28088 , H01L21/823835 , H01L29/66545 , H01L29/6656 , H01L29/7833 , H01L29/7843
摘要： A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a first MOS device of a first conductivity type and a second MOS device of a second conductivity type opposite the first conductivity type. The first MOS device includes a first gate dielectric on a semiconductor substrate; a first metal-containing gate electrode layer over the first gate dielectric; and a silicide layer over the first metal-containing gate electrode layer. The second MOS device includes a second gate dielectric on the semiconductor substrate; a second metal-containing gate electrode layer over the second gate dielectric; and a contact etch stop layer having a portion over the second metal-containing gate electrode layer, wherein a region between the portion of the contact etch stop layer and the second metal-containing gate electrode layer is substantially free from silicon.
摘要翻译：提供半导体结构及其形成方法。半导体结构包括第一导电类型的第一MOS器件和与第一导电类型相反的第二导电类型的第二MOS器件。第一MOS器件包括在半导体衬底上的第一栅极电介质; 在所述第一栅极电介质上的第一含金属的栅电极层; 以及位于第一含金属栅电极层上的硅化物层。第二MOS器件包括半导体衬底上的第二栅极电介质; 在所述第二栅极电介质上方的第二含金属的栅电极层; 以及具有位于所述第二含金属栅电极层上的部分的接触蚀刻停止层，其中所述接触蚀刻停止层的所述部分和所述第二含金属栅电极层之间的区域基本上不含硅。

2. 发明授权

US08384159B2 Semiconductor devices and methods with bilayer dielectrics 有权
标题翻译：具有双层电介质的半导体器件和方法
公开(公告)号：US08384159B2
公开(公告)日：2013-02-26
申请号：US12426477
申请日：2009-04-20
申请人： Fong-Yu Yen , Cheng-Lung Hung , Peng-Fu Hsu , Vencent S. Chang , Yong-Tian Hou , Jin Ying , Hun-Jan Tao
发明人： Fong-Yu Yen , Cheng-Lung Hung , Peng-Fu Hsu , Vencent S. Chang , Yong-Tian Hou , Jin Ying , Hun-Jan Tao
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/513 , H01L21/28088 , H01L21/28185 , H01L21/28194 , H01L29/4966 , H01L29/518
摘要： A semiconductor device is disclosed that includes: a substrate; a first dielectric layer formed over the substrate and formed of a first high-k material, the first high-k material selected from the group consisting of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfTiTaO, HfAlON, and HfZrO; a second dielectric layer formed over the first dielectric layer and formed of a second high-k material, the second high-k material being different than the first high-k material and selected from the group consisting of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfTiTaO, HfAlON, and HfZrO; and a metal gate formed over the second dielectric layer. The first dielectric layer includes ions selected from the group consisting of N, O, and Si.
摘要翻译：公开了一种半导体器件，包括：衬底; 形成在所述衬底上并由第一高k材料形成的第一介电层，所述第一高k材料选自HfO 2，HfSiO，HfSiON，HfTaO，HfTiO，HfTiTaO，HfAlON和HfZrO; 形成在所述第一介电层上并由第二高k材料形成的第二介电层，所述第二高k材料不同于所述第一高k材料并选自HfO 2，HfSiO，HfSiON，HfTaO， HfTiO，HfTiTaO，HfAlON和HfZrO; 以及形成在第二介电层上的金属栅极。第一电介质层包括选自N，O和Si的离子。

3. 发明授权

US07994051B2 Implantation method for reducing threshold voltage for high-K metal gate device 有权
标题翻译：用于降低高K金属栅极器件的阈值电压的植入方法
公开(公告)号：US07994051B2
公开(公告)日：2011-08-09
申请号：US12253741
申请日：2008-10-17
申请人： Cheng-Lung Hung , Yong-Tian Hou , Keh-Chiang Ku , Chien-Hao Huang
发明人： Cheng-Lung Hung , Yong-Tian Hou , Keh-Chiang Ku , Chien-Hao Huang
IPC分类号： H01L21/00
CPC分类号： H01L21/28088 , H01L21/265 , H01L21/268 , H01L21/32155 , H01L21/324 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a high-k dielectric layer over a semiconductor substrate, forming a capping layer over the high-k dielectric layer, forming a metal layer over the capping layer, forming a semiconductor layer over the metal layer, performing an implantation process on the semiconductor layer, the implantation process using a species including F, and forming a gate structure from the plurality of layers including the high-k dielectric layer, capping layer, metal layer, and semiconductor layer.
摘要翻译：本公开提供了制造半导体器件的方法。该方法包括在半导体衬底上形成高k电介质层，在高k电介质层上形成覆盖层，在覆盖层上形成金属层，在金属层上形成半导体层，对金属层进行注入工艺半导体层，使用包括F的物质的注入工艺，以及从包括高k电介质层，覆盖层，金属层和半导体层的多个层形成栅极结构。

4. 发明申请

US20100081262A1 METHOD FOR FORMING METAL GATES IN A GATE LAST PROCESS 有权
标题翻译：在门过程中形成金属门的方法
公开(公告)号：US20100081262A1
公开(公告)日：2010-04-01
申请号：US12411546
申请日：2009-03-26
申请人： Peng-Soon Lim , Yong-Tian Hou , Chien-Hao Chen , Chi-Chun Chen
发明人： Peng-Soon Lim , Yong-Tian Hou , Chien-Hao Chen , Chi-Chun Chen
IPC分类号： H01L21/3205 , H01L21/20 , H01L21/31
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/66583 , H01L29/66636
摘要： The present disclosure provides a method of fabricating a semiconductor device that includes providing a substrate having a first region and a second region, forming first and second gate stacks in the first and second regions, respectively, the first gate stack including a first dummy gate and the second gate stack including a second dummy gate, removing the first dummy gate in the first gate stack thereby forming a first trench and removing the second dummy gate in the second gate stack thereby forming a second trench, forming a first metal layer in the first trench and in the second trench, removing at least a portion of the first metal layer in the first trench, forming a second metal layer in the remainder of the first trench and in the remainder of the second trench, reflowing the second metal layer, and performing a chemical mechanical polishing (CMP).
摘要翻译：本公开提供一种制造半导体器件的方法，其包括提供具有第一区域和第二区域的衬底，分别在第一和第二区域中形成第一和第二栅极堆叠，第一栅极堆叠包括第一虚拟栅极和所述第二栅极堆叠包括第二伪栅极，去除所述第一栅极堆叠中的所述第一伪栅极，从而形成第一沟槽并且去除所述第二栅极堆叠中的所述第二伪栅极，从而形成第二沟槽，从而形成第一栅极堆叠中的第一金属层沟槽，并且在第二沟槽中，去除第一沟槽中的第一金属层的至少一部分，在第一沟槽的其余部分和第二沟槽的其余部分中形成第二金属层，回流第二金属层，以及进行化学机械抛光（CMP）。

5. 发明申请

US20100044804A1 NOVEL HIGH-K METAL GATE STRUCTURE AND METHOD OF MAKING 审中-公开
标题翻译：新型高K金属结构及其制备方法
公开(公告)号：US20100044804A1
公开(公告)日：2010-02-25
申请号：US12427222
申请日：2009-04-21
申请人： Chien-Hao Chen , Yong-Tian Hou , Kang-Cheng Lin , Kuo-Tai Huang
发明人： Chien-Hao Chen , Yong-Tian Hou , Kang-Cheng Lin , Kuo-Tai Huang
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L21/28088 , H01L21/28194 , H01L21/28247 , H01L29/4966 , H01L29/517 , H01L29/6659 , H01L29/7833
摘要： The present disclosure provides a semiconductor device that includes a semiconductor substrate, a transistor formed in the substrate, the transistor including a high-k gate dielectric formed over the substrate, the high-k gate dielectric having a first length measured from one sidewall to the other sidewall of the high-k gate dielectric, and a metal gate formed over the high-k gate dielectric, the metal gate having a second length measured from one sidewall to the other sidewall of the metal gate, the second length being smaller than the first length.
摘要翻译：本公开提供了一种半导体器件，其包括半导体衬底，形成在衬底中的晶体管，晶体管包括形成在衬底上的高k栅极电介质，高k栅极电介质具有从一个侧壁到高k栅极电介质的另一个侧壁和形成在高k栅极电介质上的金属栅极，金属栅极具有从金属栅极的一个侧壁到另一侧壁测量的第二长度，第二长度小于第一长。

6. 发明申请

US20080146012A1 NOVEL METHOD TO ADJUST WORK FUNCTION BY PLASMA ASSISTED METAL INCORPORATED DIELECTRIC 审中-公开
标题翻译：通过等离子体辅助金属合成电介质调整工作功能的新方法
公开(公告)号：US20080146012A1
公开(公告)日：2008-06-19
申请号：US11695227
申请日：2007-04-02
申请人： Wenli Lin , Yong-Tian Hou , Kang-Cheng Lin , Kuo-Tai Huang , Tze-Liang Lee , Mong-Song Liang
发明人： Wenli Lin , Yong-Tian Hou , Kang-Cheng Lin , Kuo-Tai Huang , Tze-Liang Lee , Mong-Song Liang
IPC分类号： H01L21/3205 , H01L21/31
CPC分类号： H01L21/3115 , H01L21/28185 , H01L21/28202 , H01L21/31155 , H01L21/3144 , H01L29/51 , H01L29/513 , H01L29/517 , H01L29/518
摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a gate dielectric on a substrate; introducing metal dopants into the gate dielectric; annealing the gate dielectric; and forming a gate electrode on the gate dielectric.
摘要翻译：本公开提供了制造半导体器件的方法。该方法包括在衬底上形成栅极电介质; 将金属掺杂剂引入栅极电介质中; 退火栅电介质; 以及在栅极电介质上形成栅电极。

7. 发明申请

US20080096336A1 Method of forming integrated circuit devices having n-MOSFET and p-MOSFET transistors with elevated and silicided source/drain structures 有权
标题翻译：形成具有n-MOSFET和p-MOSFET晶体管的集成电路器件的方法，其具有升高和硅化源极/漏极结构
公开(公告)号：US20080096336A1
公开(公告)日：2008-04-24
申请号：US11583500
申请日：2006-10-18
申请人： Peng-Soon Lim , Yong-Tian Hou , Jin Ying , Hun-Jan Tao
发明人： Peng-Soon Lim , Yong-Tian Hou , Jin Ying , Hun-Jan Tao
IPC分类号： H01L21/337
CPC分类号： H01L21/823814 , H01L21/28097 , H01L21/823807 , H01L29/66636 , H01L29/7848
摘要： An n-FET and a p-FET each have elevated source/drain structures. Optionally, the p-FET elevated-SOURCE/DRAIN structure is epitaxially grown from a p-FET recess formed in the substrate. Optionally, the n-FET elevated-SOURCE/DRAIN structure is epitaxially grown from an n-FET recess formed in the substrate. The n-FET and p-FET elevated-source/drain structures are both silicided, even though the structures may have different materials and/or different structure heights. At least a thermal treatment portion of the source/drain structure siliciding is performed simultaneously for the n-FET and p-FET elevated source/drain structures. Also, the p-FET gate electrode, the n-FET gate electrode, or both, may optionally be silicided simultaneously (same metal and/or same thermal treatment step) with the n-FET and p-FET elevated-source/drain structures, respectively; even though the gate electrodes may have different materials, different silicide metal, and/or different electrode heights. The silicides formed on n-FET and p-FET elevated-source/drain structures preferably do not extend below a top surface of the substrate more than about 250 angstroms; and the structure heights may be selected to provide this.
摘要翻译： n-FET和p-FET各自具有升高的源极/漏极结构。可选地，p-FET升高的SOURCE / DRAIN结构从形成在衬底中的p-FET凹槽外延生长。可选地，n-FET升高的SOURCE / DRAIN结构从形成在衬底中的n-FET凹槽外延生长。即使结构可能具有不同的材料和/或不同的结构高度，n-FET和p-FET升高源极/漏极结构都是硅化的。对于n-FET和p-FET升高的源极/漏极结构，至少对源极/漏极结构硅化物的热处理部分同时进行。此外，p-FET栅电极，n-FET栅电极或两者可以可选地与n-FET和p-FET升高源极/漏极结构同时（相同的金属和/或相同的热处理步骤）硅化，分别; 即使栅电极可以具有不同的材料，不同的硅化物金属和/或不同的电极高度。在n-FET和p-FET升高源极/漏极结构上形成的硅化物优选不超过约250埃延伸到衬底的顶表面下方; 并且可以选择结构高度来提供这一点。

8. 发明授权

US08679962B2 Integrated circuit metal gate structure and method of fabrication 有权
标题翻译：集成电路金属栅极结构及其制造方法
公开(公告)号：US08679962B2
公开(公告)日：2014-03-25
申请号：US12264822
申请日：2008-11-04
申请人： Yong-Tian Hou , Chien-Hao Chen , Donald Y. Chao , Cheng-Lung Hung
发明人： Yong-Tian Hou , Chien-Hao Chen , Donald Y. Chao , Cheng-Lung Hung
IPC分类号： H01L21/3205
CPC分类号： H01L29/4966 , H01L21/28088 , H01L21/28176 , H01L21/28229 , H01L29/513 , H01L29/517 , H01L29/6659 , H01L29/7833
摘要： A method of forming a gate structure is provided. The method includes providing a metal layer in the gate structure, the metal layer includes an oxygen-gettering composition. The metal layer getters oxygen from the interface layer, which may decrease the thickness of the interface layer. The gettered oxygen converts the metal layer to a metal oxide, which may act as a gate dielectric for the gate structure. A multi-layer metal gate structure is also provided including a oxygen-gettering metal layer, an oxygen-containing metal layer, and a polysilicon interface metal layer overlying a high-k gate dielectric.
摘要翻译：提供一种形成栅极结构的方法。该方法包括在栅极结构中提供金属层，金属层包括吸氧组合物。金属层从界面层吸收氧气，这可能会降低界面层的厚度。吸收的氧将金属层转化为金属氧化物，其可以用作栅极结构的栅极电介质。还提供了多层金属栅极结构，其包括吸氧过程金属层，含氧金属层和覆盖在高k栅极电介质上的多晶硅界面金属层。

9. 发明授权

US08536660B2 Hybrid process for forming metal gates of MOS devices 有权
标题翻译：用于形成MOS器件的金属栅极的混合工艺
公开(公告)号：US08536660B2
公开(公告)日：2013-09-17
申请号：US12047113
申请日：2008-03-12
申请人： Peng-Fu Hsu , Yong-Tian Hou , Ssu-Yi Li , Kuo-Tai Huang , Mong Song Liang
发明人： Peng-Fu Hsu , Yong-Tian Hou , Ssu-Yi Li , Kuo-Tai Huang , Mong Song Liang
IPC分类号： H01L21/02
CPC分类号： H01L21/823857 , H01L21/823842 , H01L27/092
摘要： A semiconductor structure includes a first MOS device including a first gate, and a second MOS device including a second gate. The first gate includes a first high-k dielectric over a semiconductor substrate; a second high-k dielectric over the first high-k dielectric; a first metal layer over the second high-k dielectric, wherein the first metal layer dominates a work-function of the first MOS device; and a second metal layer over the first metal layer. The second gate includes a third high-k dielectric over the semiconductor substrate, wherein the first and the third high-k dielectrics are formed of same materials, and have substantially a same thickness; a third metal layer over the third high-k dielectric, wherein the third metal layer and the second metal layer are formed of same materials, and have substantially a same thickness; and a fourth metal layer over the third metal layer.
摘要翻译：半导体结构包括包括第一栅极的第一MOS器件和包括第二栅极的第二MOS器件。第一栅极包括在半导体衬底上的第一高k电介质; 第一高k电介质上的第二高k电介质; 在所述第二高k电介质上的第一金属层，其中所述第一金属层支配所述第一MOS器件的功函数; 以及在所述第一金属层上的第二金属层。第二栅极包括半导体衬底上的第三高k电介质，其中第一和第三高k电介质由相同的材料形成，并具有基本上相同的厚度; 在所述第三高k电介质上的第三金属层，其中所述第三金属层和所述第二金属层由相同的材料形成，并且具有基本相同的厚度; 以及在第三金属层上的第四金属层。

10. 发明授权

US08258546B2 High-k metal gate device 有权
标题翻译：高k金属门装置
公开(公告)号：US08258546B2
公开(公告)日：2012-09-04
申请号：US13186656
申请日：2011-07-20
申请人： Cheng-Lung Hung , Yong-Tian Hou , Keh-Chiang Ku , Chien-Hao Huang
发明人： Cheng-Lung Hung , Yong-Tian Hou , Keh-Chiang Ku , Chien-Hao Huang
IPC分类号： H01L27/118
CPC分类号： H01L21/28088 , H01L21/265 , H01L21/268 , H01L21/32155 , H01L21/324 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： A semiconductor device includes a semiconductor substrate and a transistor formed in the substrate, the transistor having a gate stack that has an interfacial layer formed on the substrate, a high-k dielectric layer formed over the interfacial layer, a metal layer formed over the high-dielectric layer, a capping layer formed between the interfacial layer and high-k dielectric layer; and a doped layer formed on the metal layer, the doped layer including at least F.
摘要翻译：半导体器件包括半导体衬底和形成在衬底中的晶体管，晶体管具有栅极堆叠，其具有形成在衬底上的界面层，形成在界面层上的高k电介质层，在高层上形成的金属层 - 介电层，在界面层和高k电介质层之间形成的覆盖层; 以及形成在所述金属层上的掺杂层，所述掺杂层至少包括F.

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