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    • 1. 发明授权
    • Photomultiplier and manufacturing method thereof
    • 光电倍增管及其制造方法
    • US08871557B2
    • 2014-10-28
    • US13601948
    • 2012-08-31
    • Joon Sung LeeYong Sun Yoon
    • Joon Sung LeeYong Sun Yoon
    • H01L21/00H01L31/107
    • H01L31/107H01L27/1446H01L27/14643H01L27/14689
    • Provided are a photomultiplier and a manufacturing method thereof. The manufacturing method thereof may include forming a mask layer on an active region of a substrate doped with a first conductive type, ion implanting a second conductive type impurity opposite to the first conductive type into the substrate to form a first doped region in the active region under the mask layer and an non-active region exposed from the mask layer, forming a device isolation layer on the non-active region, removing the mask layer, and ion implanting the second conductive type impurity having a concentration higher than that of the first doped region into an upper portion of the first doped region in the active region to form a second doped region shallower than the first doped region.
    • 提供一种光电倍增管及其制造方法。 其制造方法可以包括在掺杂有第一导电类型的衬底的有源区上形成掩模层,将与第一导电类型相反的第二导电类型杂质注入到衬底中以在有源区中形成第一掺杂区 在掩模层下面和从掩模层露出的非有源区,在非有源区上形成器件隔离层,去除掩模层,以及离子注入浓度高于第一导电型杂质的第二导电型杂质 掺杂区域进入有源区域中的第一掺杂区域的上部,以形成比第一掺杂区域浅的第二掺杂区域。
    • 4. 发明授权
    • Method of fabricating T-type gate
    • 制造T型门的方法
    • US07141464B2
    • 2006-11-28
    • US11179983
    • 2005-07-12
    • Jong Moon ParkKun Sik ParkSeong Wook YooYong Sun YoonSang Gi KimYoon Kyu BaeByung Won LimJin Gun KooBo Woo Kim
    • Jong Moon ParkKun Sik ParkSeong Wook YooYong Sun YoonSang Gi KimYoon Kyu BaeByung Won LimJin Gun KooBo Woo Kim
    • H01L21/338
    • H01L21/28587
    • Provided is a method of fabricating a T-type gate including the steps of: forming a first photoresist layer, a blocking layer and a second photoresist layer to a predetermined thickness on a substrate, respectively; forming a body pattern of a T-type gate on the second photoresist layer and the blocking layer; exposing a predetermined portion of the second photoresist layer to form a head pattern of the T-type gate, and performing a heat treatment process to generate cross linking at a predetermined region of the second photoresist layer except for the head pattern of the T-type gate; performing an exposure process on an entire surface of the resultant structure, and then removing the exposed portion; and forming a metal layer of a predetermined thickness on an entire surface of the resultant structure, and then removing the first photoresist layer, the blocking layer, the predetermined region of the second photoresist layer in which the cross linking are generated, and the metal layer, whereby it is possible to readily perform a compound semiconductor device manufacturing process, and to reduce manufacturing cost by means of the increase of manufacturing yield and the simplification of manufacturing processes.
    • 提供一种制造T型栅极的方法,包括以下步骤:分别在衬底上形成预定厚度的第一光致抗蚀剂层,阻挡层和第二光致抗蚀剂层; 在所述第二光致抗蚀剂层和所述阻挡层上形成T型栅极的主体图案; 暴露第二光致抗蚀剂层的预定部分以形成T型栅极的头部图案,并且进行热处理工艺以在除了T型的头部图案之外的第二光致抗蚀剂层的预定区域处产生交联 门; 在所得结构的整个表面上进行曝光处理,然后去除所述暴露部分; 在所得结构的整个表面上形成预定厚度的金属层,然后去除第一光致抗蚀剂层,阻挡层,产生交联的第二光致抗蚀剂层的预定区域和金属层 ,由此可以容易地进行化合物半导体器件制造工艺,并且通过增加制造成品率和简化制造工艺来降低制造成本。
    • 6. 发明申请
    • CMOS-BASED PLANAR TYPE SILICON AVALANCHE PHOTO DIODE USING SILICON EPITAXIAL LAYER AND METHOD OF MANUFACTURING THE SAME
    • 使用硅外延层的基于CMOS的平面型硅氧化物照相二极管及其制造方法
    • US20090146238A1
    • 2009-06-11
    • US12195166
    • 2008-08-20
    • Yong Sun YoonKun Sik ParkJong Moon ParkBo Woo KimJin Yeong Kang
    • Yong Sun YoonKun Sik ParkJong Moon ParkBo Woo KimJin Yeong Kang
    • H01L31/103H01L31/18
    • H01L31/107
    • A complementary metal-oxide semiconductor (CMOS)-based planar type avalanche photo diode (APD) using a silicon epitaxial layer and a method of manufacturing the APD, the photo diode including: a substrate; a well layer of a first conductivity type formed in the substrate; an avalanche embedded junction formed in the well layer of the first conductivity type by low energy ion implantation; the silicon epitaxial layer formed in the avalanche embedded junction; a doping area of a second conductivity type opposite to the first conductive type, formed from a portion of a surface of the well layer of the first conductivity type in the avalanche embedded junction and forming a p-n junction; positive and negative electrodes formed on the doping area of the second conductivity type and the well layer of the first conductivity type separated from the doping area of the second conductivity type, respectively; and an oxide layer formed on an overall surface excluding a window where the positive and negative electrodes are formed.
    • 使用硅外延层的基于互补金属氧化物半导体(CMOS)的平面型雪崩光电二极管(APD)和制造该APD的方法,所述光电二极管包括:衬底; 在衬底中形成的第一导电类型的阱层; 通过低能离子注入形成在第一导电类型的阱层中的雪崩嵌入结; 形成在雪崩嵌入结的硅外延层; 由所述第一导电类型的阱层的表面的一部分形成在所述雪崩嵌入结中并形成p-n结的与所述第一导电类型相反的第二导电类型的掺杂区域; 分别形成在第二导电类型的掺杂区域上的正极和负极以及从第二导电类型的掺杂区域分离的第一导电类型的阱层; 以及形成在除了形成正极和负极的窗口之外的整个表面上的氧化物层。
    • 9. 发明授权
    • CMOS-based planar type silicon avalanche photo diode using silicon epitaxial layer and method of manufacturing the same
    • 使用硅外延层的CMOS基平面型硅雪崩光电二极管及其制造方法
    • US07994553B2
    • 2011-08-09
    • US12195166
    • 2008-08-20
    • Yong Sun YoonKun Sik ParkJong Moon ParkBo Woo KimJin Yeong Kang
    • Yong Sun YoonKun Sik ParkJong Moon ParkBo Woo KimJin Yeong Kang
    • H01L31/062
    • H01L31/107
    • A complementary metal-oxide semiconductor (CMOS)-based planar type avalanche photo diode (APD) using a silicon epitaxial layer and a method of manufacturing the APD, the photo diode including: a substrate; a well layer of a first conductivity type formed in the substrate; an avalanche embedded junction formed in the well layer of the first conductivity type by low energy ion implantation; the silicon epitaxial layer formed in the avalanche embedded junction; a doping area of a second conductivity type opposite to the first conductive type, formed from a portion of a surface of the well layer of the first conductivity type in the avalanche embedded junction and forming a p-n junction; positive and negative electrodes formed on the doping area of the second conductivity type and the well layer of the first conductivity type separated from the doping area of the second conductivity type, respectively; and an oxide layer formed on an overall surface excluding a window where the positive and negative electrodes are formed.
    • 使用硅外延层的基于互补金属氧化物半导体(CMOS)的平面型雪崩光电二极管(APD)和制造该APD的方法,所述光电二极管包括:衬底; 在衬底中形成的第一导电类型的阱层; 通过低能离子注入形成在第一导电类型的阱层中的雪崩嵌入结; 形成在雪崩嵌入结的硅外延层; 由所述第一导电类型的阱层的表面的一部分形成在所述雪崩嵌入结中并形成p-n结的与所述第一导电类型相反的第二导电类型的掺杂区域; 分别形成在第二导电类型的掺杂区域上的正极和负极以及从第二导电类型的掺杂区域分离的第一导电类型的阱层; 以及形成在除了形成正极和负极的窗口之外的整个表面上的氧化物层。