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1. 发明授权

US08592988B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08592988B2
公开(公告)日：2013-11-26
申请号：US13186049
申请日：2011-07-19
申请人： Ho-Jin Lee , Sung-Dong Cho , Se-Young Jeong , Yeong-Lyeol Park , Sin-Woo Kang
发明人： Ho-Jin Lee , Sung-Dong Cho , Se-Young Jeong , Yeong-Lyeol Park , Sin-Woo Kang
IPC分类号： H01L23/48
CPC分类号： H01L21/76898 , H01L23/481 , H01L2224/16145 , H01L2224/16225 , H01L2924/15311
摘要： A semiconductor device may include a substrate and a through electrode. The substrate may have a first surface and a second surface opposite to the first surface, the substrate including circuit patterns formed on the first surface. The through electrode penetrates the substrate and may be electrically connected to the circuit pattern, the through electrode including a first plug that extends from the first surface in a thickness direction of the substrate and a second plug that extends from the second surface in the thickness direction of the substrate so as to be connected to the first plug.
摘要翻译：半导体器件可以包括衬底和通孔。衬底可以具有与第一表面相对的第一表面和第二表面，所述衬底包括形成在第一表面上的电路图案。贯通电极穿透基板并且可以电连接到电路图案，所述通孔包括在基板的厚度方向上从第一表面延伸的第一插塞和在厚度方向上从第二表面延伸的第二插塞以便连接到第一插头。

2. 发明申请

US20120051019A1 INTERPOSER CHIP, MULTI-CHIP PACKAGE INCLUDING THE INTERPOSER CHIP, AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：插件芯片，包括插件芯片的多芯片封装及其制造方法
公开(公告)号：US20120051019A1
公开(公告)日：2012-03-01
申请号：US13215425
申请日：2011-08-23
申请人： Yeong-Lyeol Park , Sung-Dong Cho , Sin-Woo Kang
发明人： Yeong-Lyeol Park , Sung-Dong Cho , Sin-Woo Kang
IPC分类号： H05K7/06 , H05K3/22 , H01L21/50
CPC分类号： H01L22/34 , H01L23/49541 , H01L23/49822 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L25/0655 , H01L25/0657 , H01L25/18 , H01L2224/0401 , H01L2224/05009 , H01L2224/09181 , H01L2224/13025 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2225/06517 , H01L2225/06541 , H01L2225/06548 , H01L2225/06572 , H01L2225/06596 , H01L2924/1431 , H01L2924/1434 , H01L2924/15311 , H05K1/0268 , H05K7/1053 , H05K2201/10378
摘要： An interposer chip may include a substrate, a plurality of upper terminals, a plurality of lower terminals, a first conductive pattern that electrically connects the first upper terminal to a first set of one or more lower terminals, a second conductive pattern that electrically connects the second upper terminal to a second set of one or more lower terminals and a cut test pattern disposed between the first conductive pattern and the second conductive pattern, the test pattern used for testing electrical characteristics of the first conductive pattern and the second conductive pattern.
摘要翻译：插入器芯片可以包括基板，多个上端子，多个下端子，将第一上端子电连接到第一组一个或多个下端子的第一导电图案，电连接第二上端子连接到第二组一个或多个下端子，以及设置在第一导电图案和第二导电图案之间的切割测试图案，用于测试第一导电图案和第二导电图案的电特性的测试图案。

3. 发明申请

US20130052760A1 METHOD OF INSPECTING AND MANUFACTURING A STACK CHIP PACKAGE 审中-公开
标题翻译：检查和制造堆叠芯片包装的方法
公开(公告)号：US20130052760A1
公开(公告)日：2013-02-28
申请号：US13545385
申请日：2012-07-10
申请人： Sung-Dong CHO , Yeong-Lyeol PARK , Min-Seung YOON
发明人： Sung-Dong CHO , Yeong-Lyeol PARK , Min-Seung YOON
IPC分类号： H01L21/66
CPC分类号： H01L22/14 , G01R31/2853 , G01R31/2884 , G01R31/31717 , G01R31/318513 , H01L22/32 , H01L2224/16225 , H01L2224/97 , H01L2924/15192 , H01L2924/15311 , H01L2224/81
摘要： In an exemplary method of inspecting a stack chip package, a first chip is prepared. The first chip includes a through-silicon via, first pad electrodes connected to the through-silicon via and probe pad electrodes connected to the through-silicon via. A testing chip is prepared. The testing chip includes second pad electrodes that are arranged to correspond with the first pad electrodes. The testing chip is temporarily adhered to the first chip such that the second pad electrodes are electrically connected to the first pad electrode respectively, to form a stack structure wherein the probe pad electrodes are exposed to for testing. An electrical signal is applied to the exposed probe pad electrodes to test the through-silicon via included in the first chip.
摘要翻译：在检查堆叠芯片封装的示例性方法中，准备第一芯片。第一芯片包括穿硅通孔，连接到穿硅通孔的第一焊盘电极和连接到穿硅通孔的探针焊盘电极。准备了一个测试芯片。测试芯片包括被布置为与第一焊盘电极对应的第二焊盘电极。将测试芯片临时粘附到第一芯片，使得第二焊盘电极分别电连接到第一焊盘电极，以形成其中探针焊盘电极暴露以进行测试的堆叠结构。将电信号施加到暴露的探针焊盘电极，以测试包括在第一芯片中的穿硅通孔。

4. 发明申请

US20120056330A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120056330A1
公开(公告)日：2012-03-08
申请号：US13186049
申请日：2011-07-19
申请人： Ho-Jin Lee , Sung-Dong Cho , Se-Young Jeong , Yeong-Lyeol Park , Sin-Woo Kang
发明人： Ho-Jin Lee , Sung-Dong Cho , Se-Young Jeong , Yeong-Lyeol Park , Sin-Woo Kang
IPC分类号： H01L23/48
CPC分类号： H01L21/76898 , H01L23/481 , H01L2224/16145 , H01L2224/16225 , H01L2924/15311
摘要： A semiconductor device may include a substrate and a through electrode. The substrate may have a first surface and a second surface opposite to the first surface, the substrate including circuit patterns formed on the first surface. The through electrode penetrates the substrate and may be electrically connected to the circuit pattern, the through electrode including a first plug that extends from the first surface in a thickness direction of the substrate and a second plug that extends from the second surface in the thickness direction of the substrate so as to be connected to the first plug.
摘要翻译：半导体器件可以包括衬底和通孔。衬底可以具有与第一表面相对的第一表面和第二表面，所述衬底包括形成在第一表面上的电路图案。贯通电极穿透基板并且可以电连接到电路图案，所述通孔包括在基板的厚度方向上从第一表面延伸的第一插塞和在厚度方向上从第二表面延伸的第二插塞以便连接到第一插头。

5. 发明申请

US20080084223A1 TEST PATTERN AND METHOD OF MONITORING DEFECTS USING THE SAME 失效
标题翻译：测试模式和使用该方法监测缺陷的方法
公开(公告)号：US20080084223A1
公开(公告)日：2008-04-10
申请号：US11852625
申请日：2007-09-10
申请人： Hyock-Jun Lee , Choel-Hwyi Bae , Yeong-Lyeol Park , Nam-Young Lee , Mi-Joung Lee
发明人： Hyock-Jun Lee , Choel-Hwyi Bae , Yeong-Lyeol Park , Nam-Young Lee , Mi-Joung Lee
IPC分类号： G01R31/265
CPC分类号： G01R31/2884 , H01L22/34
摘要： A test pattern includes a normal pattern, an abnormal pattern having predetermined defects, and a conductive line electrically connected to the normal pattern and electrically isolated from the abnormal pattern. Thus, a non-contact test process and a contact test process may be compatible with the single test pattern.
摘要翻译：测试图案包括正常图案，具有预定缺陷的异常图案以及与正常图案电连接并与异常图案电隔离的导电线。因此，非接触测试过程和接触测试过程可以与单个测试图案兼容。

6. 发明申请

US20150130075A1 SEMICONDUCTOR PACKAGE HAVING MAGNETIC SUBSTANCE AND RELATED EQUIPMENT 有权
标题翻译：具有磁性物质和相关设备的半导体封装
公开(公告)号：US20150130075A1
公开(公告)日：2015-05-14
申请号：US14330636
申请日：2014-07-14
申请人： Sang-Wook Ji , Hyoung-Yol Mun , Yeong-Lyeol Park , In-Kyum Lee
发明人： Sang-Wook Ji , Hyoung-Yol Mun , Yeong-Lyeol Park , In-Kyum Lee
IPC分类号： H01L23/00 , H01L23/14
CPC分类号： H01L23/562 , H01L21/563 , H01L23/49816 , H01L23/49827 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L2224/10135 , H01L2224/10165 , H01L2224/13025 , H01L2224/131 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/17181 , H01L2224/73204 , H01L2224/75251 , H01L2224/75734 , H01L2224/75753 , H01L2224/81141 , H01L2224/81191 , H01L2224/94 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06575 , H01L2225/06593 , H01L2924/0002 , H01L2924/15311 , H01L2924/00 , H01L2224/81 , H01L2924/014
摘要： Provided is a semiconductor device. A semiconductor chip is disposed on a substrate. A first magnetic substance, a second magnetic substance and a third magnetic substance which are spaced apart from one another are formed on the semiconductor chip. The first magnetic substance and the second magnetic substance can be adjacent an edge of the semiconductor chip. The third magnetic substance can be adjacent a center of the semiconductor chip. The third magnetic substance is between the first magnetic substance and the second magnetic substance.
摘要翻译：提供一种半导体器件。半导体芯片设置在基板上。在半导体芯片上形成彼此间隔开的第一磁性物质，第二磁性物质和第三磁性物质。第一磁性物质和第二磁性物质可以与半导体芯片的边缘相邻。第三磁性物质可以邻近半导体芯片的中心。第三磁性物质在第一磁性物质和第二磁性物质之间。

7. 发明授权

US08729684B2 Interposer chip, multi-chip package including the interposer chip, and method of manufacturing the same 有权
标题翻译：内插芯片，包括插入片芯片的多芯片封装及其制造方法
公开(公告)号：US08729684B2
公开(公告)日：2014-05-20
申请号：US13215425
申请日：2011-08-23
申请人： Yeong-Lyeol Park , Sung-Dong Cho , Sin-Woo Kang
发明人： Yeong-Lyeol Park , Sung-Dong Cho , Sin-Woo Kang
IPC分类号： H01L23/02
CPC分类号： H01L22/34 , H01L23/49541 , H01L23/49822 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L25/0655 , H01L25/0657 , H01L25/18 , H01L2224/0401 , H01L2224/05009 , H01L2224/09181 , H01L2224/13025 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2225/06517 , H01L2225/06541 , H01L2225/06548 , H01L2225/06572 , H01L2225/06596 , H01L2924/1431 , H01L2924/1434 , H01L2924/15311 , H05K1/0268 , H05K7/1053 , H05K2201/10378
摘要： An interposer chip may include a substrate, a plurality of upper terminals, a plurality of lower terminals, a first conductive pattern that electrically connects the first upper terminal to a first set of one or more lower terminals, a second conductive pattern that electrically connects the second upper terminal to a second set of one or more lower terminals and a cut test pattern disposed between the first conductive pattern and the second conductive pattern, the test pattern used for testing electrical characteristics of the first conductive pattern and the second conductive pattern.
摘要翻译：插入器芯片可以包括基板，多个上端子，多个下端子，将第一上端子电连接到第一组一个或多个下端子的第一导电图案，电连接第二上端子连接到第二组一个或多个下端子，以及设置在第一导电图案和第二导电图案之间的切割测试图案，用于测试第一导电图案和第二导电图案的电特性的测试图案。

8. 发明申请

US20120199970A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20120199970A1
公开(公告)日：2012-08-09
申请号：US13361088
申请日：2012-01-30
申请人： Ki-Young Yun , Yeong-Lyeol PARK , Ki-Soon BAE , Woon-Seob LEE , Sung-Dong CHO , Sin-Woo KANG , Sang-Wook JI , Eun-Ji KIM
发明人： Ki-Young Yun , Yeong-Lyeol PARK , Ki-Soon BAE , Woon-Seob LEE , Sung-Dong CHO , Sin-Woo KANG , Sang-Wook JI , Eun-Ji KIM
IPC分类号： H01L23/498 , H01L21/768
CPC分类号： H01L23/5226 , H01L21/76816 , H01L21/76898 , H01L23/481 , H01L2224/13025 , H01L2224/16146
摘要： A semiconductor device includes a substrate having a via region and a circuit region, an insulation interlayer formed on a top surface of the substrate, a through electrode having a first surface and a second surface, wherein the through electrode penetrates the via region of the substrate and the second surface is substantially coplanar with a bottom surface of the substrate, a first upper wiring formed on a portion of the first surface of the through electrode, a plurality of via contacts formed on a portion of a top surface of the first upper wiring, and a second upper wiring formed on the plurality of via contacts.
摘要翻译：半导体器件包括具有通孔区域和电路区域的衬底，形成在衬底顶表面上的绝缘夹层，具有第一表面和第二表面的通孔，其中贯穿电极穿透衬底的通孔区域并且所述第二表面与所述基板的底面基本共面;形成在所述贯通电极的第一表面的一部分上的第一上布线，形成在所述第一上布线的顶表面的一部分上的多个通孔接头以及形成在所述多个通孔接触件上的第二上部布线。

9. 发明申请

US20080077269A1 METHOD AND SYSTEM FOR MANAGING WAFER PROCESSING 有权
标题翻译：管理流程处理的方法和系统
公开(公告)号：US20080077269A1
公开(公告)日：2008-03-27
申请号：US11851008
申请日：2007-09-06
申请人： Nam-young Lee , Pil-woong Bang , Yeong-lyeol Park
发明人： Nam-young Lee , Pil-woong Bang , Yeong-lyeol Park
IPC分类号： G06F19/00
CPC分类号： G05B19/4184 , G05B2219/32225 , G05B2219/34048 , G05B2219/45031 , Y02P90/14 , Y02P90/22
摘要： Disclosed are a method of managing a process and a process managing system in which a failure-generating process step can be quickly detected. The method of managing a process includes sequentially performing first to n-th (n is a natural number) process steps with respect to a plurality of wafers, the order that the plurality of wafers are processed in each of the n process steps are different from one another. Calculating characteristic parameter values for the plurality of wafers, calculating first to n-th relations that indicate relationships between the first to n-th process orders and the characteristic parameter values, performing a Fourier transform on the first to n-th relations so as to calculate first to n-th conversion relations, and determining the existence of patterns among the first to n-th relations using the first to n-th conversion relations.
摘要翻译：公开了一种管理过程和方法管理系统的方法，其中可以快速检测故障生成处理步骤。管理处理的方法包括相对于多个晶片顺序地执行第一至第n（n是自然数）处理步骤，在n个处理步骤中的每一个处理多个晶片的顺序不同于另一个。计算多个晶片的特性参数值，计算表示第一至第n处理阶数之间的关系的特征参数值的第一至第n关系，对第一至第n关系进行傅里叶变换，以便计算第一至第n转换关系，并且使用第一至第n转换关系确定第一至第n关系中的模式的存在。

10. 发明授权

US07705621B2 Test pattern and method of monitoring defects using the same 失效
标题翻译：使用相同的测试模式和监测缺陷的方法
公开(公告)号：US07705621B2
公开(公告)日：2010-04-27
申请号：US11852625
申请日：2007-09-10
申请人： Hyock-Jun Lee , Choel-Hwyi Bae , Yeong-Lyeol Park , Nam-Young Lee , Mi-Joung Lee
发明人： Hyock-Jun Lee , Choel-Hwyi Bae , Yeong-Lyeol Park , Nam-Young Lee , Mi-Joung Lee
IPC分类号： G01R31/26
CPC分类号： G01R31/2884 , H01L22/34
摘要： A test pattern includes a normal pattern, an abnormal pattern having predetermined defects, and a conductive line electrically connected to the normal pattern and electrically isolated from the abnormal pattern. Thus, a non-contact test process and a contact test process may be compatible with the single test pattern.
摘要翻译：测试图案包括正常图案，具有预定缺陷的异常图案以及与正常图案电连接并与异常图案电隔离的导电线。因此，非接触测试过程和接触测试过程可以与单个测试图案兼容。

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