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    • 7. 发明授权
    • Semiconductor memory test apparatus
    • 半导体存储器测试装置
    • US6144596A
    • 2000-11-07
    • US188410
    • 1998-11-10
    • Yeong Chang Ahn
    • Yeong Chang Ahn
    • G01R31/28G01R31/3185G11C7/10G11C7/22G11C11/401G11C11/407G11C29/00G11C29/02G11C29/46G11C29/50G11C7/00
    • G11C29/028G11C29/02G11C29/46G11C29/50G11C29/50012G11C7/1045G11C7/22G11C11/401
    • A semiconductor memory test apparatus includes a test signal input unit for externally receiving a test word line model signal and a test column address pulse enable signal, which are used for a memory operation in the test mode. The test apparatus also includes a test mode setting unit that receives: a row address strobe bar signal, a column address strobe bar signal, a write enable bar signal and an address signal, and that generates first and second test mode setting signals. A first switching unit switches a signal input from a row address path circuit or from the test signal input unit, in accordance with a first test mode setting signal. A second switching unit switches another signal input from the row address path circuit or from the test signal input unit in accordance with a second test mode setting signal, and outputs the switched signal to the column address path circuit.
    • 半导体存储器测试装置包括用于外部接收测试字线模型信号的测试信号输入单元和用于测试模式中的存储器操作的测试列地址脉冲使能信号。 测试装置还包括测试模式设置单元,其接收行地址选通信号,列地址选通信号,写使能条信号和地址信号,并且产生第一和第二测试模式设置信号。 第一切换单元根据第一测试模式设置信号切换来自行地址路径电路或来自测试信号输入单元的信号。 第二切换单元根据第二测试模式设置信号切换从行地址​​路径电路或测试信号输入单元输入的另一个信号,并将切换的信号输出到列地址路径电路。