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1. 发明授权

US5210053A Method for fabricating semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US5210053A
公开(公告)日：1993-05-11
申请号：US846083
申请日：1992-03-05
申请人： Yasushi Yamagata
发明人： Yasushi Yamagata
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/768 , H01L23/52
CPC分类号： H01L21/76802
摘要： A method for fabricating a semiconductor device includes steps of forming wirings on the surface of a semiconductor substrate with a plurality of diffused layers; forming a first insulating film whose surface is flattened; forming a first group of contact holes having substantially the same depth reaching the diffused layers and the wirings; embedding selectively grown conductive layers in the first group of contact holes; depositing a second insulating film on the entire surface; forming , in the first insulating film and the second insulating film, a second group of contact holes having substantially the same depth reaching the other of the diffused layers and the wirings; and embedding selectively grown conductive layers in the second group of contact holes. A plurality of contact holes with different depths formed in an interlayer insulating film are grouped into two or more groups in accordance with their depth, and are filled with contact materials selectively grown by individual processes so that the surface of the contacts thus formed can be made completely flat. Thus, regardless of the thickness of the interlayer insulating film formed on a chip, stabilized wirings can be made with good coverage for the contacts so that the reliability of the completed semiconductor device can be greatly enhanced.
摘要翻译：一种制造半导体器件的方法包括以下步骤：在具有多个扩散层的半导体衬底的表面上形成布线; 形成表面平坦化的第一绝缘膜; 形成具有与扩散层和布线基本相同的深度的第一组接触孔; 在第一组接触孔中嵌入选择性地生长的导电层; 在整个表面上沉积第二绝缘膜; 在所述第一绝缘膜和所述第二绝缘膜中形成具有与所述扩散层和所述布线中的另一个基本相同的深度的第二组接触孔; 以及在所述第二组接触孔中嵌入选择性地生长的导电层。在层间绝缘膜中形成的具有不同深度的多个接触孔根据其深度分为两组或更多组，并且填充有通过单独工艺选择性生长的接触材料，使得可以制成如此形成的触点的表面完全平坦因此，不管形成在芯片上的层间绝缘膜的厚度如何，可以对触点进行良好的覆盖，从而可以大大提高完整的半导体器件的可靠性。

2. 发明授权

US09069923B2 IP protection 有权
标题翻译：知识产权保护
公开(公告)号：US09069923B2
公开(公告)日：2015-06-30
申请号：US13161514
申请日：2011-06-16
申请人： Soon Yoeng Tan , Teck Jung Tang , Ian D. Melville , Yelei Vianna Yao , Yasushi Yamagata
发明人： Soon Yoeng Tan , Teck Jung Tang , Ian D. Melville , Yelei Vianna Yao , Yasushi Yamagata
IPC分类号： G06F17/50 , G06F7/06 , G06F1/00 , H01L29/66
CPC分类号： H01L27/0207 , G06F17/5068 , G06F2217/66 , H01L22/32
摘要： Multi-Project Wafers includes a plurality of chiplets from different IP owners. Non-relevant chiplets are implemented with IP protection to inhibit IP disclosure of non-relevant IP owners.
摘要翻译：多项目晶片包括来自不同IP所有者的多个小芯片。采用知识产权保护措施实施不相关的小白鼠，以防止非相关知识产权拥有者的知识产权披露。

3. 发明授权

US5535158A Non-volatile semiconductor memory device and method for erasure and production thereof 失效
标题翻译：非易失性半导体存储器件及其擦除和制造方法
公开(公告)号：US5535158A
公开(公告)日：1996-07-09
申请号：US350978
申请日：1994-11-29
申请人： Yasushi Yamagata
发明人： Yasushi Yamagata
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , G11C16/12 , G11C16/14 , H01L21/8247 , H01L27/092 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792 , G11C7/00
CPC分类号： H01L27/11526 , G11C16/12 , G11C16/14 , H01L27/0922 , H01L27/105 , H01L27/11546 , H01L29/7885
摘要： A non-volatile memory cell disclosed herein includes a pair of regions are provided in a channel region in contact respectively with source and drain to provide a symmetrical structure. A data erase is done by applying a high voltage to the source to produce avalanche breakdown between the source and the region to inject induced hot carriers into the floating gate and wherein the memory cell threshold voltage after erasure is converged to a constant value irrespective of the initial states, while the converged value may be controlled to a desired voltage by applying a suitable voltage to the control gate. Erasure sequence consisting in all bit erase and one verification is sufficient such that the erase sequence is simplified and erase time shortened.
摘要翻译：本文公开的非易失性存储单元包括一对区域，其设置在与源极和漏极分别接触的沟道区域中以提供对称结构。通过向源施加高电压以在源极和区域之间产生雪崩击穿以将感应的热载流子注入到浮动栅极中，并且其中擦除之后的存储单元阈值电压被收敛到恒定值，而不管初始状态，而可以通过向控制栅极施加合适的电压来将收敛值控制到期望的电压。包括所有位擦除和一个验证的擦除序列是足够的，使得擦除序列被简化并且擦除时间缩短。

4. 发明授权

US5441595A Dry etching apparatus and method of forming a via hole in an interlayer insulator using same 失效
标题翻译：干法蚀刻装置及使用该蚀刻装置的层间绝缘体中形成通孔的方法
公开(公告)号：US5441595A
公开(公告)日：1995-08-15
申请号：US238370
申请日：1994-05-05
申请人： Yasushi Yamagata , Fumihide Sato
发明人： Yasushi Yamagata , Fumihide Sato
IPC分类号： C23F4/00 , H01J37/32 , H01L21/302 , H01L21/3065 , H01L21/311 , H01L21/3213 , H01L21/768 , B44C1/22
CPC分类号： H01J37/32192 , H01J37/32587 , H01J37/32678 , H01J37/32706 , H01L21/31116 , H01L21/76804
摘要： In order to cyclically implement isotropical and anisotropical etching of an interlayer insulator provided in a semiconductor wafer, two variable capacitors are provided for applying RF bias (power) to a triode type dry etching apparatus. The two variable capacitors are controlled such that cyclically, as one of the two capacitors exhibits maximum capacitance thereof, the other capacitor exhibits minimum capacitance thereof. As an alternative to the above, a wafer supporting table provided in a reactive chamber of an electron cyclotron resonance type apparatus, is cyclically supplied with a radio frequency (RF) bias and the ground potential. This cyclic application of the RF bias and the ground potential is controlled by a combination of a pulse generator and an amplitude modulation circuit both coupled to an RF signal generator. The via hole is effectively formed using the cyclic operations of the isotropic and anisotropic etching.
摘要翻译：为了周期性地实施设置在半导体晶片中的层间绝缘体的等温和各向异性蚀刻，提供了两个可变电容器，用于将三极管型干法蚀刻装置的RF偏压（功率）施加。两个可变电容器被控制为使得循环地，由于两个电容器中的一个表现出最大电容，所以另一个电容器表现出最小的电容。作为上述的替代，设置在电子回旋共振型装置的反应室中的晶片支撑台被周期性地提供射频（RF）偏置和地电位。 RF偏置和接地电位的这种循环应用由两个耦合到RF信号发生器的脉冲发生器和幅度调制电路的组合来控制。使用各向同性和各向异性蚀刻的循环操作有效地形成通孔。

5. 发明授权

US5282160A Non-volatile semiconductor memory having double gate structure 失效
标题翻译：具有双栅极结构的非易失性半导体存储器
公开(公告)号：US5282160A
公开(公告)日：1994-01-25
申请号：US732146
申请日：1991-07-18
申请人： Yasushi Yamagata
发明人： Yasushi Yamagata
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/68 , H01L29/78
CPC分类号： H01L27/115
摘要： A double gate non-volatile semiconductor memory comprises a plurality of device isolation regions formed of an insulator material filled into a plurality of trenches formed in a substrate, so that a device formation region is formed between each pair of adjacent device isolation regions. A side wall of an insulator material is formed to cover side surfaces of floating gates and word lines formed on the floating gates, which extend in a direction orthogonal to the direction of the device formation region. Source regions and drain regions are formed by doping impurity into the device formation regions surrounded by the side wall. A plurality of common source lines of a low resistance conductor film are formed each to extend in the orthogonal direction so as to pass on the source regions positioned in each one row of the orthogonal direction. Thus, the word lines are surely isolated from the source lines.
摘要翻译：双栅极非易失性半导体存储器包括由填充到形成在衬底中的多个沟槽中的绝缘体材料形成的多个器件隔离区域，从而在每对相邻器件隔离区域之间形成器件形成区域。绝缘体材料的侧壁被形成为覆盖形成在浮动栅极上的浮动栅极和字线的侧表面，其在与器件形成区域的方向正交的方向上延伸。通过将杂质掺杂到由侧壁包围的器件形成区域中来形成源极区和漏极区。形成低电阻导体膜的多个公共源极线，每个沿正交方向延伸，以便在位于正交方向的每一行中的源极区域上通过。因此，字线肯定地与源极线隔离。

6. 发明授权

US5070378A EPROM erasable by UV radiation having redundant circuit 失效
标题翻译：通过具有冗余电路的紫外线辐射可擦除EPROM
公开(公告)号：US5070378A
公开(公告)日：1991-12-03
申请号：US679146
申请日：1991-03-28
申请人： Yasushi Yamagata
发明人： Yasushi Yamagata
IPC分类号： H01L21/8247 , H01L21/82 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , H01L29/7881
摘要： A semiconductor device includes a shield layer selectively formed to cover, via an insulating film, source and drain regions, a control gate electrode, first and second conductive layers and parts of first, second and third polycrystalline silicon layers. The shield layer has a portion which is in contact with the semiconductor substrate and the third polycrystalline silicon layer to surround the source and drain regions, floating and control gate electrodes, the first and second conductive layers and the parts of the first and second polycrystalline silicon layers.

7. 发明申请

US20120319246A1 IP PROTECTION 有权
标题翻译： IP保护
公开(公告)号：US20120319246A1
公开(公告)日：2012-12-20
申请号：US13161514
申请日：2011-06-16
申请人： Soon Yoeng TAN , Teck Jung TANG , Ian D. MELVILLE , Yelei Vianna YAO , Yasushi YAMAGATA
发明人： Soon Yoeng TAN , Teck Jung TANG , Ian D. MELVILLE , Yelei Vianna YAO , Yasushi YAMAGATA
IPC分类号： H01L29/06 , G06F17/50
CPC分类号： H01L27/0207 , G06F17/5068 , G06F2217/66 , H01L22/32
摘要： Multi-Project Wafers includes a plurality of chiplets from different IP owners. Non-relevant chiplets are implemented with IP protection to inhibit IP disclosure of non-relevant IP owners.
摘要翻译：多项目晶片包括来自不同IP所有者的多个小芯片。采用知识产权保护措施实施不相关的小白鼠，以防止非相关知识产权拥有者的知识产权披露。

8. 发明授权

US5362358A Dry etching apparatus and method of forming a via hole in an interlayer insulator using same 失效
标题翻译：干法蚀刻装置及使用该蚀刻装置的层间绝缘体中形成通孔的方法
公开(公告)号：US5362358A
公开(公告)日：1994-11-08
申请号：US61440
申请日：1993-05-14
申请人： Yasushi Yamagata , Fumihide Sato
发明人： Yasushi Yamagata , Fumihide Sato
IPC分类号： C23F4/00 , H01J37/32 , H01L21/302 , H01L21/3065 , H01L21/311 , H01L21/3213 , H01L21/768 , B44C1/22
CPC分类号： H01J37/32192 , H01J37/32587 , H01J37/32678 , H01J37/32706 , H01L21/31116 , H01L21/76804
摘要： In order to cyclically implement isotropical and anisotropical etching of an interlayer insulator provided in a semiconductor wafer, two variable capacitors are provided for applying RF bias (power) to a triode type dry etching apparatus. The two variable capacitors are controlled such that cyclically, as one of the two capacitors exhibits maximum capacitance thereof, the other capacitor exhibits minimum capacitance thereof. As an alternative to the above, a wafer supporting table provided in a reactive chamber of an electron cyclotron resonance type apparatus, is cyclically supplied with a radio frequency (RF) bias and the ground potential. This cyclic application of the RF bias and the ground potential is controlled by a combination of a pulse generator and an amplitude modulation circuit both coupled to an RF signal generator. The via hole is effectively formed using the cyclic operations of the isotropic and anisotropic etching.
摘要翻译：为了周期性地实施设置在半导体晶片中的层间绝缘体的等温和各向异性蚀刻，提供了两个可变电容器，用于将三极管型干法蚀刻装置的RF偏压（功率）施加。两个可变电容器被控制为使得循环地，由于两个电容器中的一个表现出最大电容，所以另一个电容器表现出最小的电容。作为上述的替代，设置在电子回旋共振型装置的反应室中的晶片支撑台被周期性地提供射频（RF）偏置和地电位。 RF偏置和接地电位的这种循环应用由两个耦合到RF信号发生器的脉冲发生器和幅度调制电路的组合来控制。使用各向同性和各向异性蚀刻的循环操作有效地形成通孔。

9. 发明授权

US5677875A Non-volatile semiconductor memory device configured to minimize variations in threshold voltages of non-written memory cells and potentials of selected bit lines 失效
标题翻译：非易失性半导体存储器件被配置为最小化非写入存储器单元的阈值电压的变化和所选位线的电位
公开(公告)号：US5677875A
公开(公告)日：1997-10-14
申请号：US606860
申请日：1996-02-26
申请人： Yasushi Yamagata , Masakazu Amanai
发明人： Yasushi Yamagata , Masakazu Amanai
IPC分类号： G11C16/08 , G11C16/10 , G11C7/00
CPC分类号： G11C16/3427 , G11C16/08 , G11C16/10
摘要： A non-volatile semiconductor memory device is provided in which a variation of threshold voltages of non-written memory cells and a potential variation of a selected bit line in preventing generation of drain disturb phenomenon are minimized Source lines SL.sub.1 ', SL.sub.2 ', SL.sub.3 ' and SL.sub.4 ' are provided in parallel to word lines WL.sub.1, WL.sub.2, WL.sub.3 and WL.sub.4, respectively, and selectively. When a data is to be written in a memory cell C.sub.11, a potential of a selected word line WL.sub.1 is set to a high voltage V.sub.pp, potentials of non-selected word lines WL.sub.2, WL.sub.3 and WL.sub.4 are set to the drain disturb preventing voltage, for example, an intermediate voltage V.sub.pp /2 which is a half of the high voltage. Further, a potential of a selected bit line BL.sub.1 is set to a potential V.sub.dd which is lower than the high voltage V.sub.pp, non-selected bit lines BL.sub.2, BL.sub.3 and BL.sub.4 are made open. Further, a potential of a selected source line SL.sub.1 ' is set to the ground potential GND and the non-selected source lines SL.sub.2 ', SL.sub.3 ' and SL.sub.4 ' are made open.
摘要翻译：提供一种非易失性半导体存储器件，其中非写入存储器单元的阈值电压的变化和所选位线的电位变化防止漏极干扰现象的产生被最小化源极线SL1'，SL2'，SL3' 和SL4'分别并行地设置在字线WL1，WL2，WL3和WL4上。当要将数据写入存储单元C11中时，将所选字线WL1的电位设置为高电压Vpp，将未选择的字线WL2，WL3和WL4的电位设置为漏极干扰防止电压，例如，作为高电压的一半的中间电压Vpp / 2。此外，选择的位线BL1的电位被设置为低于高压Vpp的电位Vdd，未选择的位线BL2，BL3和BL4被打开。此外，将选择的源极线SL1'的电位设置为接地电位GND，使未选择的源极线SL2'，SL3'和SL4'断开。

10. 发明授权

US5331592A Non-volatile semiconductor memory device with erasure control circuit 失效
标题翻译：具有擦除控制电路的非易失性半导体存储器件
公开(公告)号：US5331592A
公开(公告)日：1994-07-19
申请号：US62396
申请日：1993-05-17
申请人： Yasushi Yamagata
发明人： Yasushi Yamagata
IPC分类号： H01L21/8247 , G11C16/16 , G11C16/34 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/40
CPC分类号： G11C16/3477 , G11C16/16 , G11C16/3468
摘要： A non-volatile semiconductor memory device has an erasure control circuit which, during erasure operation, is switched to a source of a memory cell having a floating gate. The erasure control circuit is constituted by a resistor element and a reference transistor having the same structure as that of the memory cell. One end of the resistor element is connected to a node which, during erasure operation, is electrically connected to the source of the memory cell. The reference transistor has a drain connected to the node, a gate connected to a constant-voltage source, and a source grounded. A floating gate/substrate insulating film of the memory cell and a floating gate/substrate insulating film of the reference transistor are formed simultaneously in the same fabrication step so that the thickness of these insulating films are substantially the same. Even when the thickness of the floating gate/substrate insulating film of the memory cell varies due to production variations, it is possible to prevent the occurrence of an over-erase or a deficient erase by making changes accordingly in the erasure voltage, that is, the voltage at the node.
摘要翻译：非易失性半导体存储器件具有擦除控制电路，其在擦除操作期间切换到具有浮动栅极的存储单元的源极。擦除控制电路由具有与存储单元相同结构的电阻元件和参考晶体管构成。电阻元件的一端连接到在擦除操作期间电连接到存储单元的源的节点。参考晶体管具有连接到节点的漏极，连接到恒定电压源的栅极和源极接地。存储单元的浮栅/衬底绝缘膜和参考晶体管的浮栅/衬底绝缘膜在相同的制造步骤中同时形成，使得这些绝缘膜的厚度基本相同。即使当存储单元的浮栅/衬底绝缘膜的厚度由于生产变化而变化时，也可以通过在擦除电压中相应地改变来防止发生过擦除或擦除不足，即，节点处的电压。

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