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1. 发明授权

US08122306B2 Test circuit for supporting concurrent test mode in a semiconductor memory 失效
标题翻译：用于在半导体存储器中支持并发测试模式的测试电路
公开(公告)号：US08122306B2
公开(公告)日：2012-02-21
申请号：US12144522
申请日：2008-06-23
申请人： Woo-Hyun Seo
发明人： Woo-Hyun Seo
IPC分类号： G11C29/00 , G01R31/00
CPC分类号： G01R31/31701
摘要： A test circuit is capable of simultaneously performing various test modes. The test circuit includes a concurrent test mode controller for providing a plurality of decoding signals by receiving test mode input signals while test modes are being activated, and simultaneously providing the decoding signals if predetermined concurrent test mode signals are received.
摘要翻译：测试电路能够同时执行各种测试模式。测试电路包括并发测试模式控制器，用于通过在测试模式被激活时接收测试模式输入信号来提供多个解码信号，并且如果接收到预定的同时测试模式信号，则同时提供解码信号。

2. 发明授权

US07920417B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07920417B2
公开(公告)日：2011-04-05
申请号：US12494344
申请日：2009-06-30
申请人： Woo-Hyun Seo , Kwang-Myoung Rho
发明人： Woo-Hyun Seo , Kwang-Myoung Rho
IPC分类号： G11C11/14
CPC分类号： G11C11/16 , G11C7/062 , G11C7/067 , G11C11/1659 , G11C11/1673
摘要： A semiconductor memory cell includes a plurality of memory cells configured to store data having polarity corresponding to a direction of current flowing in first and second driving lines, a current generator configured to generate a predetermined read current, apply the predetermined read current to the plurality of memory cells, and generate a data current corresponding variation of the read current according to the data and a current controller connected to a current path of the read current and configured to control a current amount of the read current.
摘要翻译：半导体存储单元包括：多个存储单元，被配置为存储具有对应于在第一和第二驱动线中流动的电流的方向的极性的数据;电流发生器，被配置为产生预定的读取电流;将预定的读取电流施加到多个存储单元，并根据该数据产生与读取电流相对应的变化的数据电流，以及连接到读取电流的当前路径并被配置为控制读取电流的当前量的电流控制器。

3. 发明申请

US20100125431A1 COMPACT TEST CIRCUIT AND INTEGRATED CIRCUIT HAVING THE SAME 审中-公开
标题翻译：紧凑的测试电路和具有该测试电路的集成电路
公开(公告)号：US20100125431A1
公开(公告)日：2010-05-20
申请号：US12427901
申请日：2009-04-22
申请人： Woo-Hyun SEO
发明人： Woo-Hyun SEO
IPC分类号： G06F19/00
CPC分类号： G11C29/14 , G11C29/12015 , G11C29/46
摘要： A compact test circuit prevents a chip area increase by reducing the number of global lines, i.e., transmission paths of test mode item signals. The test circuit is capable of reducing a test time by performing several tests in parallel through one test mode item signal. The test circuit includes a test mode item signal generating block configured to generate a plurality of test mode item signals corresponding to test mode items, and a coding block configured to code each of the test mode item signals to generate a multiplicity of test control signals.
摘要翻译：紧凑的测试电路通过减少全局线的数量，即测试模式项目信号的传输路径来防止芯片面积增加。测试电路能够通过一个测试模式项目信号并行执行多个测试来减少测试时间。测试电路包括测试模式项目信号产生模块，被配置为产生与测试模式项目相对应的多个测试模式项目信号;以及编码模块，被配置为对每个测试模式项目信号进行编码以产生多个测试控制信号。

4. 发明申请

US20090006917A1 TEST CIRCUIT FOR SUPPORTING CONCURRENT TEST MODE IN A SEMICONDUCTOR MEMORY 失效
标题翻译：用于支持半导体存储器中的并流测试模式的测试电路
公开(公告)号：US20090006917A1
公开(公告)日：2009-01-01
申请号：US12144522
申请日：2008-06-23
申请人： Woo Hyun Seo
发明人： Woo Hyun Seo
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/31701
摘要： A test circuit is capable of simultaneously performing various test modes. The test circuit includes a concurrent test mode controller for providing a plurality of decoding signals by receiving test mode input signals while test modes are being activated, and simultaneously providing the decoding signals if predetermined concurrent test mode signals are received.
摘要翻译：测试电路能够同时执行各种测试模式。测试电路包括并发测试模式控制器，用于通过在测试模式被激活时接收测试模式输入信号来提供多个解码信号，并且如果接收到预定的同时测试模式信号，则同时提供解码信号。

5. 发明申请

US20080163018A1 TEST CONTROL CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME 失效
标题翻译：测试控制电路和包括其的半导体存储器件
公开(公告)号：US20080163018A1
公开(公告)日：2008-07-03
申请号：US11777523
申请日：2007-07-13
申请人： Woo Hyun SEO
发明人： Woo Hyun SEO
IPC分类号： G06F11/267
CPC分类号： G06F11/263 , G01R31/31724
摘要： The present invention relates to a test control circuit controlling a test of an internal circuit and a semiconductor memory device including the same. The present invention provides a test control circuit having: an encoding unit encoding test mode signals input from the external and transferring them to global lines; a decoding unit decoding the signals transferred from the global lines; and a test mode enable signal generating circuit generating test mode enable signals controlling a test mode enable by combining the output signals of the decoding unit and an address designating a test mode item code.
摘要翻译：本发明涉及一种控制内部电路测试的测试控制电路和包括该测试控制电路的半导体存储器件。本发明提供了一种测试控制电路，具有：编码单元，编码从外部输入的测试模式信号并将其传送到全局线; 解码单元，对从全局线路传送的信号进行解码; 以及测试模式使能信号发生电路，通过组合解码单元的输出信号和指定测试模式项目代码的地址，生成测试模式使能信号来控制测试模式使能。

6. 发明申请

US20070121746A1 Apparatus and method for dynamic channel allocation with low complexity in a multi-carrier communication system 审中-公开
标题翻译：在多载波通信系统中具有低复杂度的动态信道分配的装置和方法
公开(公告)号：US20070121746A1
公开(公告)日：2007-05-31
申请号：US11605070
申请日：2006-11-28
申请人： Myeon-Kyun Cho , Jong-Hyeuk Lee , Jong-Hyung Kwun , Woo-Hyun Seo , Daesik Hong
发明人： Myeon-Kyun Cho , Jong-Hyeuk Lee , Jong-Hyung Kwun , Woo-Hyun Seo , Daesik Hong
IPC分类号： H04K1/10
CPC分类号： H04L27/2608 , H04L5/023
摘要： A low-complexity dynamic channel allocation apparatus and method in a multi-carrier communication system are provided. In the low-complexity dynamic channel allocation method, subcarriers are initially allocated to total users and two users are selected from among all possible cases of two users out of the total users. The power gain of each of the subcarriers initially allocated to the selected two users is calculated, which can be generated by reallocating each subcarrier to the other user through subcarrier swapping. The power gains of the initially allocated subcarriers are ordered for each of the selected users and a pair of subcarriers with the greatest power gains for the two users are selected. Subcarriers are reallocated to the two users by swapping the selected subcarriers between the two users.
摘要翻译：提供了一种多载波通信系统中的低复杂度动态信道分配装置和方法。在低复杂度动态信道分配方法中，初始分配副载波到总用户，并且从总用户中的两个用户的所有可能情况中选择两个用户。计算最初分配给所选择的两个用户的每个子载波的功率增益，其可以通过通过子载波交换将每个子载波重新分配给另一个用户而产生。为每个所选择的用户排序初始分配的子载波的功率增益，并且选择两个用户具有最大功率增益的一对子载波。通过在两个用户之间交换所选择的子载波来将子载波重新分配给两个用户。

7. 发明授权

US07767596B2 Wafer support pin for preventing slip dislocation during annealing of water and wafer annealing method using the same 有权
标题翻译：用于防止水退火期间的滑脱错位的晶片支撑销和使用其的晶片退火方法
公开(公告)号：US07767596B2
公开(公告)日：2010-08-03
申请号：US12005415
申请日：2007-12-26
申请人： Kun Kim , Jin-Kyun Hong , Woo-Hyun Seo , Kyoung-Hwan Song
发明人： Kun Kim , Jin-Kyun Hong , Woo-Hyun Seo , Kyoung-Hwan Song
IPC分类号： H01L21/26
CPC分类号： H01L21/6875 , H01L21/68757
摘要： A wafer support pin has a front end contacted with a wafer such that the front end is flat or rounded. Thus, gravitational stress is minimized during annealing the wafer, thereby minimizing slip dislocation. This wafer support pin is suitably used for annealing of a wafer, particularly high temperature rapid thermal annealing of a large-diameter wafer.
摘要翻译：晶片支撑销具有与晶片接触的前端，使得前端是平坦的或圆形的。因此，在退火晶片期间重力应力最小化，从而最小化滑动位错。该晶片支撑销适合用于晶片退火，特别是大直径晶片的高温快速热退火。

8. 发明申请

US20090096500A1 SKEW COMPENSATION CIRCUIT 失效
标题翻译： SKEW补偿电路
公开(公告)号：US20090096500A1
公开(公告)日：2009-04-16
申请号：US12205261
申请日：2008-09-05
申请人： Woo Hyun SEO , Yong Ho KONG
发明人： Woo Hyun SEO , Yong Ho KONG
IPC分类号： H03K5/12
CPC分类号： H03K5/12
摘要： The present invention describes a skew compensation circuit that can compensate for changes in signal skew in response to changes in external environments and processes. The skew compensation circuit includes a controller for outputting a control signal according to whether an external power supply is supplied and its operation mode. The skew compensation circuit also includes a signal output unit which selects either a normal path or a skew reduction path according to the control signal and outputs an input signal through the selected path.
摘要翻译：本发明描述了一种可以补偿响应于外部环境和过程变化的信号偏差变化的偏斜补偿电路。偏斜补偿电路包括：控制器，用于根据外部电源是否提供控制信号及其运行模式来输出。偏斜补偿电路还包括根据控制信号选择正常路径或偏斜减少路径的信号输出单元，并通过所选路径输出输入信号。

9. 发明授权

US08067969B2 Integrated circuit 失效
标题翻译：集成电路
公开(公告)号：US08067969B2
公开(公告)日：2011-11-29
申请号：US12493774
申请日：2009-06-29
申请人： Woo-Hyun Seo
发明人： Woo-Hyun Seo
IPC分类号： H03K5/12
CPC分类号： H03K19/00384
摘要： An integrated circuit includes a pull-up compensation path unit configured to adjust a pull-up driving power of an input signal; a pull-down compensation path unit configured to adjust a pull-down driving power of the input signal; and a path control unit configured to route the input signal to one of the pull-up compensation unit and the pull-down compensation unit in response to a conditional signal.
摘要翻译：集成电路包括被配置为调整输入信号的上拉驱动功率的上拉补偿路径单元; 配置为调整所述输入信号的下拉驱动功率的下拉补偿路径单元; 以及路径控制单元，被配置为响应于条件信号将输入信号路由到上拉补偿单元和下拉补偿单元中的一个。

10. 发明授权

US08036026B2 Semiconductor memory device and method for operating the same 有权
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US08036026B2
公开(公告)日：2011-10-11
申请号：US12488069
申请日：2009-06-19
申请人： Kwang-Myoung Rho , Woo-Hyun Seo
发明人： Kwang-Myoung Rho , Woo-Hyun Seo
IPC分类号： G11C11/14
CPC分类号： G11C7/12 , G11C11/1653 , G11C11/1659 , G11C11/1675
摘要： A semiconductor memory device includes a plurality of memory cells configured to store data having a polarity corresponding to a direction of current flowing through a source line and a bit line; and a precharge driving unit configured to precharge the bit line to a voltage corresponding to the data in response to a precharging signal before the data are stored in the memory cells.
摘要翻译：半导体存储器件包括多个存储器单元，其被配置为存储具有与流过源极线和位线的电流的方向相对应的极性的数据; 以及预充电驱动单元，被配置为在将数据存储在存储单元中之前，根据预充电信号将位线预充电到对应于该数据的电压。

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