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1. 发明授权

US09376713B2 Label free detection of nucleic acid amplification 有权
标题翻译：无标记检测核酸扩增
公开(公告)号：US09376713B2
公开(公告)日：2016-06-28
申请号：US12888917
申请日：2010-09-23
申请人： Rashid Bashir , Yi-Shao Liu , Eric Salm , Woo-Jin Chang , Nicholas N. Watkins
发明人： Rashid Bashir , Yi-Shao Liu , Eric Salm , Woo-Jin Chang , Nicholas N. Watkins
IPC分类号： C12Q1/68 , B01L3/00 , B01L7/00 , B03C5/02 , B01L3/02
CPC分类号： C12Q1/6825 , B01L3/0241 , B01L3/5027 , B01L3/502746 , B01L3/502761 , B01L3/502784 , B01L7/52 , B01L2200/0668 , B01L2200/10 , B01L2200/143 , B01L2200/147 , B01L2300/0645 , B01L2300/0681 , B01L2300/0867 , B01L2300/1822 , B01L2300/1827 , B01L2400/0418 , B01L2400/0424 , B01L2400/084 , B03C5/026
摘要： Provided are methods and devices for label-free detection of nucleic acids that are amplified by polymerase chain reaction. A solution containing the components necessary for a PCR is introduced to a microfluidic amplification chamber and an electric field applied to a confined region in which PCR occurs. PCR product generated in the confined region is detected by measuring an electrical parameter that is, for example, solution impedance. The devices and methods provided herein are used, for example, in assays to detect one or more pathogens or for point-of-care tests. In an aspect, the PCR product is confined to droplets and the assay relates to detecting an electrical parameter of a flowing droplet, thereby detecting PCR product without a label. In an aspect, the PCR occurs in the droplet.
摘要翻译：提供了通过聚合酶链反应扩增的用于无标记检测核酸的方法和装置。将含有PCR所需组分的溶液引入微流体扩增室，并施加到发生PCR的限制区域的电场。通过测量例如溶液阻抗的电参数来检测在限制区域中产生的PCR产物。本文提供的装置和方法例如用于检测一种或多种病原体或用于点护理测试的测定中。在一方面，PCR产物被限制在液滴中，并且该测定涉及检测流动液滴的电参数，从而检测没有标签的PCR产物。在一方面，PCR在液滴中发生。

2. 发明授权

US08723222B2 Nitride electronic device and method for manufacturing the same 有权
标题翻译：氮化物电子器件及其制造方法
公开(公告)号：US08723222B2
公开(公告)日：2014-05-13
申请号：US13548522
申请日：2012-07-13
申请人： Sung Bum Bae , Eun Soo Nam , Jae Kyoung Mun , Sung Bock Kim , Hae Cheon Kim , Chull Won Ju , Sang Choon Ko , Jong-Won Lim , Ho Kyun Ahn , Woo Jin Chang , Young Rak Park
发明人： Sung Bum Bae , Eun Soo Nam , Jae Kyoung Mun , Sung Bock Kim , Hae Cheon Kim , Chull Won Ju , Sang Choon Ko , Jong-Won Lim , Ho Kyun Ahn , Woo Jin Chang , Young Rak Park
IPC分类号： H01L31/102
CPC分类号： H01L29/66446 , H01L21/0242 , H01L21/02458 , H01L21/0254 , H01L21/02647 , H01L21/8252 , H01L27/0605 , H01L27/0883
摘要： The present disclosure relates to a nitride electronic device and a method for manufacturing the same, and particularly, to a nitride electronic device and a method for manufacturing the same that can implement various types of nitride integrated structures on the same substrate through a regrowth technology (epitaxially lateral over-growth: ELOG) of a semi-insulating gallium nitride (GaN) layer used in a III-nitride semiconductor electronic device including Group III elements such as gallium (Ga), aluminum (Al) and indium (In) and nitrogen.
摘要翻译：本发明涉及一种氮化物电子器件及其制造方法，特别涉及一种氮化物电子器件及其制造方法，该氮化物电子器件及其制造方法可以通过再生技术在同一衬底上实现各种氮化物一体化结构（用于包括III族元素如镓（Ga），铝（Al）和铟（In））和氮（III）的III族氮化物半导体电子器件中的半绝缘氮化镓（GaN）层的外延横向过度生长：ELOG）。

3. 发明申请

US20130020649A1 NITRIDE ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：氮化物电子器件及其制造方法
公开(公告)号：US20130020649A1
公开(公告)日：2013-01-24
申请号：US13548522
申请日：2012-07-13
申请人： Sung Bum BAE , Eun Soo NAM , Jae Kyoung MUN , Sung Bock KIM , Hae Cheon KIM , Chull Won JU , Sang Choon KO , Jong-Won LIM , Ho Kyun AHN , Woo Jin CHANG , Young Rak PARK
发明人： Sung Bum BAE , Eun Soo NAM , Jae Kyoung MUN , Sung Bock KIM , Hae Cheon KIM , Chull Won JU , Sang Choon KO , Jong-Won LIM , Ho Kyun AHN , Woo Jin CHANG , Young Rak PARK
IPC分类号： H01L27/088 , H01L21/20 , H01L27/08
CPC分类号： H01L29/66446 , H01L21/0242 , H01L21/02458 , H01L21/0254 , H01L21/02647 , H01L21/8252 , H01L27/0605 , H01L27/0883
摘要： The present disclosure relates to a nitride electronic device and a method for manufacturing the same, and particularly, to a nitride electronic device and a method for manufacturing the same that can implement various types of nitride integrated structures on the same substrate through a regrowth technology (epitaxially lateral over-growth: ELOG) of a semi-insulating gallium nitride (GaN) layer used in a III-nitride semiconductor electronic device including Group III elements such as gallium (Ga), aluminum (Al) and indium (In) and nitrogen.
摘要翻译：本发明涉及一种氮化物电子器件及其制造方法，特别涉及一种氮化物电子器件及其制造方法，该氮化物电子器件及其制造方法可以通过再生技术在同一衬底上实现各种氮化物一体化结构（用于包括III族元素如镓（Ga），铝（Al）和铟（In））和氮（III）的III族氮化物半导体电子器件中的半绝缘氮化镓（GaN）层的外延横向过度生长：ELOG）。

4. 发明授权

US07387955B2 Field effect transistor and method for manufacturing the same 有权
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US07387955B2
公开(公告)日：2008-06-17
申请号：US11454721
申请日：2006-06-16
申请人： Ho Kyun Ahn , Jong Won Lim , Jae Kyoung Mun , Hong Gu Ji , Woo Jin Chang , Hea Cheon Kim
发明人： Ho Kyun Ahn , Jong Won Lim , Jae Kyoung Mun , Hong Gu Ji , Woo Jin Chang , Hea Cheon Kim
IPC分类号： H01L21/44
CPC分类号： H01L29/812 , H01L29/42316 , H01L29/66462 , H01L29/66856 , H01L29/778
摘要： A field effect transistor having a T- or Γ-shaped fine gate electrode of which a head portion is wider than a foot portion, and a method for manufacturing the field effect transistor, are provided. A void is formed between the head portion of the gate electrode and a semiconductor substrate using an insulating layer having a multi-layer structure with different etch rates. Since parasitic capacitance between the gate electrode and the semiconductor substrate is reduced by the void, the head portion of the gate electrode can be made large so that gate resistance can be reduced. In addition, since the height of the gate electrode can be adjusted by adjusting the thickness of the insulating layer, device performance as well as process uniformity and repeatability can be improved.
摘要翻译：提供具有头部比脚部宽的T形或γ形的精细栅电极的场效应晶体管，以及制造场效应晶体管的方法。使用具有不同蚀刻速率的多层结构的绝缘层，在栅电极的头部和半导体衬底之间形成空隙。由于栅电极和半导体衬底之间的寄生电容由于空隙而减小，所以能够使栅电极的头部大，能够降低栅极电阻。此外，由于可以通过调节绝缘层的厚度来调节栅电极的高度，因此可以提高器件性能以及工艺的均匀性和重复性。

5. 发明授权

US07183149B2 Method of manufacturing field effect transistor 有权
标题翻译：制造场效应晶体管的方法
公开(公告)号：US07183149B2
公开(公告)日：2007-02-27
申请号：US11180726
申请日：2005-07-14
申请人： Ho Kyun Ahn , Jong Won Lim , Hong Gu Ji , Woo Jin Chang , Jae Kyoung Mun , Hae Cheon Kim
发明人： Ho Kyun Ahn , Jong Won Lim , Hong Gu Ji , Woo Jin Chang , Jae Kyoung Mun , Hae Cheon Kim
IPC分类号： H01L21/338
CPC分类号： H01L29/66856 , H01L29/66462
摘要： Provided is a method of manufacturing a field effect transistor (FET). The method includes steps of: forming an ohmic metal layer on a substrate in source and drain regions; sequentially forming an insulating layer and a multilayered resist layer on the entire surface of the resultant structure and simultaneously forming resist patterns having respectively different shapes in both a first region excluding the ohmic metal layer and a second region excluding the ohmic metal layer, wherein a lowermost resist pattern is exposed in the first region, and the insulating layer is exposed in the second region; exposing the substrate and the insulating layer by simultaneously etching the exposed insulating layer and the exposed lowermost resist pattern using the resist patterns as etch masks, respectively; performing a recess process on the exposed substrate and etching the exposed insulating layer to expose the substrate; and forming gate recess regions having different etching depths from each other over the substrate, depositing a predetermined gate metal, and removing the resist patterns. In this method, transistors having different threshold voltages can be manufactured without additional mask patterns using the least number of processes, with the results that the cost of production can be reduced and the stability and productivity of semiconductor devices can be improved.
摘要翻译：提供了制造场效应晶体管（FET）的方法。该方法包括以下步骤：在源极和漏极区域的衬底上形成欧姆金属层; 在所得结构的整个表面上顺序地形成绝缘层和多层抗蚀剂层，并且同时形成除了欧姆金属层以外的第一区域和不包括欧姆金属层的第二区域中具有不同形状的抗蚀剂图案，其中最下面抗蚀剂图案在第一区域中暴露，并且绝缘层在第二区域中暴露; 通过分别使用抗蚀剂图案作为蚀刻掩模，同时蚀刻暴露的绝缘层和暴露的最下面的抗蚀剂图案来暴露衬底和绝缘层; 对曝光的衬底进行凹陷处理并蚀刻暴露的绝缘层以露出衬底; 以及在衬底上形成具有彼此不同蚀刻深度的栅极凹陷区域，沉积预定的栅极金属和去除抗蚀剂图案。在该方法中，可以使用最少数量的工艺来制造具有不同阈值电压的晶体管，而不需要额外的掩模图案，结果可以降低生产成本，并且可以提高半导体器件的稳定性和生产率。

6. 发明授权

US08058658B2 High-speed optical interconnection device 有权
标题翻译：高速光互连装置
公开(公告)号：US08058658B2
公开(公告)日：2011-11-15
申请号：US12421130
申请日：2009-04-09
申请人： Sang-Heung Lee , Hae Cheon Kim , Dong Min Kang , Dong-Young Kim , Jae Kyoung Mun , Hokyun Ahn , Jong-Won Lim , Woo Jin Chang , Hong Gu Ji , Eun Soo Nam
发明人： Sang-Heung Lee , Hae Cheon Kim , Dong Min Kang , Dong-Young Kim , Jae Kyoung Mun , Hokyun Ahn , Jong-Won Lim , Woo Jin Chang , Hong Gu Ji , Eun Soo Nam
IPC分类号： H01L27/15
CPC分类号： H01L25/167 , H01L2224/0603 , H01L2224/45014 , H01L2224/48137 , H01L2224/4903 , H01L2224/73265 , H01L2924/1305 , H01L2924/30107 , H01L2924/00
摘要： Provided is a high-speed optical interconnection device. The high-speed optical interconnection device includes a first semiconductor chip, light emitters, optical detectors, and a second semiconductor chip, which are disposed on a silicon-on-insulator (SOI) substrate. The light emitters receive electrical signals from the first semiconductor chip to output optical signals. The optical detectors detect the optical signals to convert the optical signals into electrical signals. The second semiconductor chip receives the electrical signals converted by the optical detectors.
摘要翻译：提供了一种高速光互连装置。高速光互连装置包括设置在绝缘体上硅（SOI））衬底上的第一半导体芯片，发光体，光检测器和第二半导体芯片。光发射器接收来自第一半导体芯片的电信号以输出光信号。光检测器检测光信号，将光信号转换为电信号。第二半导体芯片接收由光学检测器转换的电信号。

7. 发明申请

US20100133551A1 HIGH-SPEED OPTICAL INTERCONNECTION DEVICE 有权
标题翻译：高速光学互连器件
公开(公告)号：US20100133551A1
公开(公告)日：2010-06-03
申请号：US12421130
申请日：2009-04-09
申请人： Sang-Heung Lee , Hae Cheon Kim , Dong Min Kang , Dong-Young Kim , Jae-Kyoung Mun , Hokyun Ahn , Jong-Won Lim , Woo Jin Chang , Hong Gu Ji , Eun Soo Nam
发明人： Sang-Heung Lee , Hae Cheon Kim , Dong Min Kang , Dong-Young Kim , Jae-Kyoung Mun , Hokyun Ahn , Jong-Won Lim , Woo Jin Chang , Hong Gu Ji , Eun Soo Nam
IPC分类号： H01L31/147 , H01L33/00
CPC分类号： H01L25/167 , H01L2224/0603 , H01L2224/45014 , H01L2224/48137 , H01L2224/4903 , H01L2224/73265 , H01L2924/1305 , H01L2924/30107 , H01L2924/00
摘要： Provided is a high-speed optical interconnection device. The high-speed optical interconnection device includes a first semiconductor chip, light emitters, optical detectors, and a second semiconductor chip, which are disposed on a silicon-on-insulator (SOI) substrate. The light emitters receive electrical signals from the first semiconductor chip to output optical signals. The optical detectors detect the optical signals to convert the optical signals into electrical signals. The second semiconductor chip receives the electrical signals converted by the optical detectors.
摘要翻译：提供了一种高速光互连装置。高速光互连装置包括设置在绝缘体上硅（SOI））衬底上的第一半导体芯片，发光体，光检测器和第二半导体芯片。光发射器接收来自第一半导体芯片的电信号以输出光信号。光检测器检测光信号，将光信号转换为电信号。第二半导体芯片接收由光学检测器转换的电信号。

8. 发明申请

US20090146184A1 SEMICONDUCTOR DEVICE WITH T-GATE ELECTRODE AND METHOD FOR FABRICATING THE SAME 失效
标题翻译：具有T型电极的半导体器件及其制造方法
公开(公告)号：US20090146184A1
公开(公告)日：2009-06-11
申请号：US12122982
申请日：2008-05-19
申请人： Jong Won LIM , Ho Kyun AHN , Hong Gu JI , Woo Jin CHANG , Jae Kyoung MUN , Hae Cheon KIM , Hyun Kyu YU
发明人： Jong Won LIM , Ho Kyun AHN , Hong Gu JI , Woo Jin CHANG , Jae Kyoung MUN , Hae Cheon KIM , Hyun Kyu YU
IPC分类号： H01L29/812 , H01L21/335
CPC分类号： H01L29/778 , H01L29/20 , H01L29/42316 , H01L29/66462
摘要： Provided are a semiconductor device with a T-gate electrode capable of improving stability and a high frequency characteristic of the semiconductor device by reducing source resistance, parasitic capacitance, and gate resistance and a method of fabricating the same. In the semiconductor device, in order to form source and drain electrodes and the T-gate electrode on a substrate, first and second protective layers constructed with silicon oxide layers or silicon nitride layers are formed on sides of a supporting part under a head part of the T-gate electrode, and the second protective layer constructed with a silicon oxide layer or silicon nitride layer is formed on sides of the source and drain electrodes. Accordingly, it is possible to protect an activated region of the semiconductor device and reduce gate-drain parasitic capacitance and gate-source parasitic capacitance.
摘要翻译：提供一种具有T栅电极的半导体器件及其制造方法，该半导体器件能够通过降低源极电阻，寄生电容和栅极电阻来提高半导体器件的稳定性和高频特性。在半导体器件中，为了在衬底上形成源电极和漏电极以及T栅电极，在氧化硅层或氮化硅层构成的第一和第二保护层形成在支撑部分的头部在栅电极和漏电极的侧面上形成T形栅电极和由氧化硅层或氮化硅层构成的第二保护层。因此，可以保护半导体器件的激活区域并减小栅极 - 漏极寄生电容和栅极 - 源极寄生电容。

9. 发明授权

US07429894B2 Power device having connection structure compensating for reactance component of transmission line 失效
标题翻译：具有补偿传输线电抗分量的连接结构的功率器件
公开(公告)号：US07429894B2
公开(公告)日：2008-09-30
申请号：US11519668
申请日：2006-09-12
申请人： Woo Jin Chang , Jae Kyoung Mun , Haecheon Kim , Jong Won Lim , Hong Gu Ji , Ho Kyun Ahn
发明人： Woo Jin Chang , Jae Kyoung Mun , Haecheon Kim , Jong Won Lim , Hong Gu Ji , Ho Kyun Ahn
IPC分类号： H03F3/68
CPC分类号： H03F3/602 , H03F3/211 , H03F2200/366 , H03F2200/447 , H03F2200/543 , H03F2203/21178
摘要： Provided is a power device having a connection structure compensating for a reactance component, in which transistors are arranged and connected to minimize deterioration of transistor properties caused by heat by compensating for a reactance component causing a phase difference due to transmission lines used for connecting a plurality of transistors in parallel such that the power device to be used for a high-frequency power amplifier outputs high power, and transmitting heat generated by high output power to a heat sink to be dissipated.
摘要翻译：提供了具有补偿电抗分量的连接结构的功率器件，其中配置并连接晶体管，以通过补偿导致由于用于连接多个元件的传输线引起的相位差的电抗分量来最小化由热引起的晶体管性质的劣化的晶体管并联，使得用于高频功率放大器的功率器件输出高功率，并将由高输出功率产生的热量传输到散热器。

10. 发明授权

US07106153B2 Waveguide interconnection apparatus 有权
标题翻译：波导互连设备
公开(公告)号：US07106153B2
公开(公告)日：2006-09-12
申请号：US10788435
申请日：2004-03-01
申请人： Woo Jin Chang , Hea Cheon Kim
发明人： Woo Jin Chang , Hea Cheon Kim
IPC分类号： H01P1/02
CPC分类号： H01P1/022 , H01P1/042
摘要： Provided is a waveguide interconnection apparatus making rectangular interconnecting portions to be a curved structure, whereby it is possible to reduce a signal reflection and a signal loss due to a mismatch occurred from a discontinuous portion where waveguides are perpendicularly connected to each other, and fabricate package products having excellent performances compared to that of the prior art in the same chip and structure.
摘要翻译：提供一种使矩形互连部分成为弯曲结构的波导互连装置，由此可以减少信号反射和由波导彼此垂直连接的不连续部分发生的失配引起的信号丢失，并且制造封装产品在相同的芯片和结构中具有优于现有技术的性能。

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