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1. 发明授权

US07605472B2 Interconnections having double capping layer and method for forming the same 有权
标题翻译：具有双层覆盖层的互连及其形成方法
公开(公告)号：US07605472B2
公开(公告)日：2009-10-20
申请号：US11706885
申请日：2007-02-15
申请人： Kyoung-woo Lee , Soo-geun Lee , Ki-chul Park , Won-sang Song
发明人： Kyoung-woo Lee , Soo-geun Lee , Ki-chul Park , Won-sang Song
IPC分类号： H01L29/40
CPC分类号： H01L21/76832 , H01L21/76807 , H01L21/76834 , H01L21/76843 , H01L21/76873 , H01L21/76874 , H01L21/76877 , H01L21/76883 , H01L23/53228 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer on a copper layer processed by chemical mechanical polishing (CMP). Therefore, it is possible to maintain a high etching selectivity and a low dielectric constant of the silicon carbide layer while providing superior leakage suppression.
摘要翻译：提供了包括封盖层和形成互连的方法的半导体器件的互连。半导体器件的互连是铜镶嵌互连，其中覆盖层形成为通过化学机械抛光（CMP）处理的铜层上的氮化硅层和碳化硅层的双层。因此，可以在提供优异的泄漏抑制的同时保持碳化硅层的高蚀刻选择性和低介电常数。

2. 发明申请

US20070138642A1 Interconnections having double capping layer and method for forming the same 有权
标题翻译：具有双层覆盖层的互连及其形成方法
公开(公告)号：US20070138642A1
公开(公告)日：2007-06-21
申请号：US11706885
申请日：2007-02-15
申请人： Kyoung-woo Lee , Soo-geun Lee , Ki-chul Park , Won-sang Song
发明人： Kyoung-woo Lee , Soo-geun Lee , Ki-chul Park , Won-sang Song
IPC分类号： H01L23/52 , H01L23/48
CPC分类号： H01L21/76832 , H01L21/76807 , H01L21/76834 , H01L21/76843 , H01L21/76873 , H01L21/76874 , H01L21/76877 , H01L21/76883 , H01L23/53228 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer on a copper layer processed by chemical mechanical polishing (CMP). Therefore, it is possible to maintain a high etching selectivity and a low dielectric constant of the silicon carbide layer while providing superior leakage suppression.
摘要翻译：提供了包括封盖层和形成互连的方法的半导体器件的互连。半导体器件的互连是铜镶嵌互连，其中覆盖层形成为通过化学机械抛光（CMP）处理的铜层上的氮化硅层和碳化硅层的双层。因此，可以在提供优异的泄漏抑制的同时保持碳化硅层的高蚀刻选择性和低介电常数。

3. 发明授权

US07205666B2 Interconnections having double capping layer and method for forming the same 有权
公开(公告)号：US07205666B2
公开(公告)日：2007-04-17
申请号：US11367790
申请日：2006-03-03
申请人： Kyoung-woo Lee , Soo-geun Lee , Ki-chul Park , Won-sang Song
发明人： Kyoung-woo Lee , Soo-geun Lee , Ki-chul Park , Won-sang Song
IPC分类号： H01L29/40
CPC分类号： H01L21/76832 , H01L21/76807 , H01L21/76834 , H01L21/76843 , H01L21/76873 , H01L21/76874 , H01L21/76877 , H01L21/76883 , H01L23/53228 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer on a copper layer processed by chemical mechanical polishing (CMP). Therefore, it is possible to maintain a high etching selectivity and a low dielectric constant of the silicon carbide layer while providing superior leakage suppression.

4. 发明授权

US06580134B1 Field effect transistors having elevated source/drain regions 失效
标题翻译：具有升高的源极/漏极区域的场效应晶体管
公开(公告)号：US06580134B1
公开(公告)日：2003-06-17
申请号：US09680805
申请日：2000-10-06
申请人： Won-sang Song , Jung-woo Park , Gil-gwang Lee , Tae-hee Choe
发明人： Won-sang Song , Jung-woo Park , Gil-gwang Lee , Tae-hee Choe
IPC分类号： H01L2976
CPC分类号： H01L29/66628 , H01L29/665 , H01L29/66545 , H01L29/66636
摘要： Field effect transistors (FETs) include an integrated circuit substrate having a surface, and a gate on the surface. A pair of recessed regions in the substrate are located beneath the surface. Respective ones of the recessed regions are located on respective opposite sides of the gate. Each of the recessed regions define a sidewall and a floor. An elevated source/drain structure on each of the recessed regions is at least as thick adjacent to the gate as remote from the gate. A gate spacer may be included between the gate and the elevated source/drain region. The gate spacer can comprise an insulating film. Preferably, the source/drain structure extends to the sidewall of the recessed region. The elevated source/drain structure is preferably free of a facet adjacent the gate. The present invention also relates to methods for fabricating a field effect transistors (FET) having an elevated source/drain structure. These methods may comprise the steps of: providing a integrated circuit substrate having a surface and a gate on the integrated circuit substrate; subsequently removing portions of the integrated circuit substrate to form a pair of recessed regions below the surface of the integrated circuit substrate, the recessed region being defined by a floor and sidewall in the integrated circuit substrate; and epitaxially growing a layer on the floor and sidewall of each recessed region.
摘要翻译：场效应晶体管（FET）包括具有表面的集成电路基板和表面上的栅极。衬底中的一对凹陷区域位于表面下方。凹陷区域中的各个位于门的相应的相对侧上。凹陷区域中的每一个限定了侧壁和底板。每个凹陷区域上的升高的源极/漏极结构至少与栅极相邻的栅极远离栅极一样厚。栅极间隔物可以包括在栅极和升高的源极/漏极区域之间。栅极隔离物可以包括绝缘膜。优选地，源极/漏极结构延伸到凹陷区域的侧壁。升高的源极/漏极结构优选没有邻近栅极的刻面。本发明还涉及用于制造具有升高的源极/漏极结构的场效应晶体管（FET）的方法。这些方法可以包括以下步骤：提供在集成电路基板上具有表面和栅极的集成电路基板; 随后去除所述集成电路基板的部分，以在所述集成电路基板的表面下方形成一对凹陷区域，所述凹陷区域由所述集成电路基板中的底板和侧壁限定; 并且在每个凹陷区域的地板和侧壁上外延生长一层。

5. 发明授权

US06511888B1 Method of fabricating a semiconductor device using trench isolation method including hydrogen annealing step 失效
公开(公告)号：US06511888B1
公开(公告)日：2003-01-28
申请号：US09697302
申请日：2000-10-27
申请人： Tai-su Park , Kyung-won Park , Jung-woo Park , Won-sang Song
发明人： Tai-su Park , Kyung-won Park , Jung-woo Park , Won-sang Song
IPC分类号： H01L21336
CPC分类号： H01L21/76224 , Y10S438/958
摘要： A method of fabricating a semiconductor device using a trench isolation method including a hydrogen annealing step, wherein a photoresist pattern is formed on a semiconductor substrate, a pad insulating layer may be formed before forming the photoresist pattern, the semiconductor substrate is etched using the photoresist pattern as an etching mask to form a trench, and an isolation layer is formed in the trench. To remove damages created in an active region defined by the isolation layer, the semiconductor substrate having the isolation layer is annealed in a hydrogen atmosphere.

6. 发明授权

US07951712B2 Interconnections having double capping layer and method for forming the same 有权
标题翻译：具有双层覆盖层的互连及其形成方法
公开(公告)号：US07951712B2
公开(公告)日：2011-05-31
申请号：US12556094
申请日：2009-09-09
申请人： Kyoung-woo Lee , Soo-geun Lee , Ki-chul Park , Won-sang Song
发明人： Kyoung-woo Lee , Soo-geun Lee , Ki-chul Park , Won-sang Song
IPC分类号： H01L21/44
CPC分类号： H01L21/76832 , H01L21/76807 , H01L21/76834 , H01L21/76843 , H01L21/76873 , H01L21/76874 , H01L21/76877 , H01L21/76883 , H01L23/53228 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer on a copper layer processed by chemical mechanical polishing (CMP). Therefore, it is possible to maintain a high etching selectivity and a low dielectric constant of the silicon carbide layer while providing superior leakage suppression.
摘要翻译：提供了包括封盖层和形成互连的方法的半导体器件的互连。半导体器件的互连是铜镶嵌互连，其中覆盖层形成为通过化学机械抛光（CMP）处理的铜层上的氮化硅层和碳化硅层的双层。因此，可以在提供优异的泄漏抑制的同时保持碳化硅层的高蚀刻选择性和低介电常数。

7. 发明申请

US20100003814A1 Interconnections Having Double Capping Layer and Method for Forming the Same 有权
标题翻译：具有双顶盖层的互连及其形成方法
公开(公告)号：US20100003814A1
公开(公告)日：2010-01-07
申请号：US12556094
申请日：2009-09-09
申请人： Kyoung-woo Lee , Soo-geun Lee , Ki-chul Park , Won-sang Song
发明人： Kyoung-woo Lee , Soo-geun Lee , Ki-chul Park , Won-sang Song
IPC分类号： H01L21/768
CPC分类号： H01L21/76832 , H01L21/76807 , H01L21/76834 , H01L21/76843 , H01L21/76873 , H01L21/76874 , H01L21/76877 , H01L21/76883 , H01L23/53228 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer on a copper layer processed by chemical mechanical polishing (CMP). Therefore, it is possible to maintain a high etching selectivity and a low dielectric constant of the silicon carbide layer while providing superior leakage suppression.
摘要翻译：提供了包括封盖层和形成互连的方法的半导体器件的互连。半导体器件的互连是铜镶嵌互连，其中覆盖层形成为通过化学机械抛光（CMP）处理的铜层上的氮化硅层和碳化硅层的双层。因此，可以在提供优异的泄漏抑制的同时保持碳化硅层的高蚀刻选择性和低介电常数。

8. 发明授权

US06690187B2 Apparatus for testing reliability of interconnection in integrated circuit 有权
标题翻译：集成电路中互连可靠性的装置
公开(公告)号：US06690187B2
公开(公告)日：2004-02-10
申请号：US10114735
申请日：2002-04-01
申请人： Won-Sang Song , Jung-Woo Kim , Chang-Sub Lee , Sam-Young Kim , Young-Jin Wee , Ki-Chul Park
发明人： Won-Sang Song , Jung-Woo Kim , Chang-Sub Lee , Sam-Young Kim , Young-Jin Wee , Ki-Chul Park
IPC分类号： G01R3102
CPC分类号： G01R31/2853
摘要： In the present invention, an apparatus of testing a leakage protection reliability of an integrated circuit interconnection. The apparatus has at least one comb-like pattern, a serpentine-like pattern and means of applying a bias to the patterns and forms a maximum field region at an interconnection formed around a via, i.e., at the end of a tooth portion composing the comb-like pattern. In one structure of the present invention, the comb-like pattern is formed at one level, and the serpentine-like pattern has a plurality of unit parts corresponding to the tooth portions, respectively, and connection parts connecting the neighboring two unit parts. Each of the unit parts is formed at the same level with the comb-like pattern and spaced apart from the tooth portion by a minimum design length according to a design rule. The unit part has vias formed through an interlayer dielectric layer at the both ends of a tooth parallel part, two tooth parallel parts connected with the vias, respectively, and a length parallel part electrically connecting two tooth parallel parts.
摘要翻译：在本发明中，一种测试集成电路互连的漏电保护可靠性的装置。该装置具有至少一个梳状图案，蛇形样图案和向图案施加偏压的装置，并且在形成在通孔周围的互连处形成最大场区域，即构成梳状图案在本发明的一个结构中，梳状图案形成在一个层面上，并且蛇形状图案分别具有对应于齿部的多个单位部分和连接相邻两个单元部分的连接部分。根据设计规则，每个单元部分与梳状图案形成在相同的高度上，并且与齿部分距离最小设计长度。单元部分具有通过在平行部分的两端处的层间绝缘层形成的通孔，分别与通孔连接的两个齿平行部分和电连接两个齿平行部分的长度平行部分。

9. 发明授权

US06645866B2 Method of fabricating a semiconductor device using trench isolation method including hydrogen annealing step 失效
标题翻译：使用包括氢退火步骤的沟槽隔离方法制造半导体器件的方法
公开(公告)号：US06645866B2
公开(公告)日：2003-11-11
申请号：US10319534
申请日：2002-12-16
申请人： Tai-su Park , Kyung-won Park , Jung-woo Park , Won-sang Song
发明人： Tai-su Park , Kyung-won Park , Jung-woo Park , Won-sang Song
IPC分类号： H01L2176
CPC分类号： H01L21/76224 , Y10S438/958
摘要： A method of fabricating a semiconductor device using a trench isolation method including a hydrogen annealing step, wherein a photoresist pattern is formed on a semiconductor substrate, a pad insulating layer may be formed before forming the photoresist pattern, the semiconductor substrate is etched using the photoresist pattern as an etching mask to form a trench, and an isolation layer is formed in the trench. To remove damages created in an active region defined by the isolation layer, the semiconductor substrate having the isolation layer is annealed in a hydrogen atmosphere.
摘要翻译：使用包括氢退火步骤的沟槽隔离方法制造半导体器件的方法，其中在半导体衬底上形成光致抗蚀剂图案，可以在形成光致抗蚀剂图案之前形成衬垫绝缘层，使用光致抗蚀剂蚀刻半导体衬底图案作为蚀刻掩模以形成沟槽，并且在沟槽中形成隔离层。为了消除在由隔离层限定的有源区域中产生的损伤，具有隔离层的半导体衬底在氢气氛中退火。

10. 发明授权

US06881630B2 Methods for fabricating field effect transistors having elevated source/drain regions 有权
标题翻译：制造具有升高的源极/漏极区域的场效应晶体管的方法
公开(公告)号：US06881630B2
公开(公告)日：2005-04-19
申请号：US10426509
申请日：2003-04-30
申请人： Won-sang Song , Jung-woo Park , Gil-gwang Lee , Tae-hee Choe
发明人： Won-sang Song , Jung-woo Park , Gil-gwang Lee , Tae-hee Choe
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66628 , H01L29/665 , H01L29/66545 , H01L29/66636
摘要： Field effect transistors (FETs) include an integrated circuit substrate having a surface, and a gate on the surface. A pair of recessed regions in the substrate are located beneath the surface. Respective ones of the recessed regions are located on respective opposite sides of the gate. Each of the recessed regions define a sidewall and a floor. An elevated source/drain structure on each of the recessed regions is at least as thick adjacent to the gate as remote from the gate. A gate spacer may be included between the gate and the elevated source/drain region. The gate spacer can comprise an insulating film. Preferably, the source/drain structure extends to the sidewall of the recessed region. The elevated source/drain structure is preferably free of a facet adjacent the gate. The present invention also relates to methods for fabricating a field effect transistors (FET) having an elevated source/drain structure. These methods may comprise the steps of: providing a integrated circuit substrate having surface and a gate on the integrated circuit substrate; subsequently removing portions of the integrated circuit substrate to form a pair of recessed regions below the surface of the integrated circuit substrate, the recessed region being defined by a floor and sidewall in the integrated circuit substrate; and epitaxially growing a layer on the floor and sidewall of each recessed region.
摘要翻译：场效应晶体管（FET）包括具有表面的集成电路基板和表面上的栅极。衬底中的一对凹陷区域位于表面下方。凹陷区域中的各个位于门的相应的相对侧上。凹陷区域中的每一个限定了侧壁和底板。每个凹陷区域上的升高的源极/漏极结构至少与栅极相邻的栅极远离栅极一样厚。栅极间隔物可以包括在栅极和升高的源极/漏极区域之间。栅极隔离物可以包括绝缘膜。优选地，源极/漏极结构延伸到凹陷区域的侧壁。升高的源极/漏极结构优选没有邻近栅极的刻面。本发明还涉及用于制造具有升高的源极/漏极结构的场效应晶体管（FET）的方法。这些方法可以包括以下步骤：在集成电路基板上提供具有表面和栅极的集成电路基板; 随后去除所述集成电路基板的部分，以在所述集成电路基板的表面下方形成一对凹陷区域，所述凹陷区域由所述集成电路基板中的底板和侧壁限定; 并且在每个凹陷区域的地板和侧壁上外延生长一层。

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