专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07750378B2 Field effect transistor and method of fabricating the same 有权
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US07750378B2
公开(公告)日：2010-07-06
申请号：US11400520
申请日：2006-04-10
申请人： Won-ju Cho , Chang-geun Ahn , Ki-ju Im , Jong-heon Yang , In-bok Baek , Seong-jae Lee
发明人： Won-ju Cho , Chang-geun Ahn , Ki-ju Im , Jong-heon Yang , In-bok Baek , Seong-jae Lee
IPC分类号： H01L29/78
CPC分类号： H01L29/7835 , H01L29/41783 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/66659 , H01L29/7834
摘要： Provided are a field effect transistor and a method of fabricating the same, wherein the field effect transistor is formed which has a hyperfine channel length by employing a technique for forming a sidewall spacer and adjusting the deposition thickness of a thin film. In the field effect transistor of the present invention, a source junction and a drain junction are thin, and the overlap between the source and the gate and between the drain and the gate is prevented, thereby lowering parasitic resistance. Further, the gate electric field is easily introduced to the drain extending region, so that the carrier concentration is effectively controlled in the channel at the drain. Also, the drain extending region is formed to be thinner than the source, so that the short channel characteristic is excellent.
摘要翻译：提供一种场效应晶体管及其制造方法，其中通过采用用于形成侧壁间隔物的技术和调节薄膜的沉积厚度，形成具有超精细沟道长度的场效应晶体管。在本发明的场效应晶体管中，源极结和漏极结很薄，并且防止源极和栅极之间以及漏极和栅极之间的重叠，从而降低寄生电阻。此外，栅极电场容易地被引入到漏极延伸区域，使得在漏极的沟道中有效地控制载流子浓度。此外，漏极延伸区域形成为比源极薄，使得短沟道特性优异。

2. 发明授权

US07060580B2 Field effect transistor and method of fabricating the same 有权
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US07060580B2
公开(公告)日：2006-06-13
申请号：US11125101
申请日：2005-05-10
申请人： Won-ju Cho , Chang-geun Ahn , Ki-ju Im , Jong-heon Yang , In-bok Baek , Seong-jae Lee
发明人： Won-ju Cho , Chang-geun Ahn , Ki-ju Im , Jong-heon Yang , In-bok Baek , Seong-jae Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/7835 , H01L29/41783 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/66659 , H01L29/7834
摘要： Provided are a field effect transistor and a method of fabricating the same, wherein the field effect transistor is formed which has a hyperfine channel length by employing a technique for forming a sidewall spacer and adjusting the deposition thickness of a thin film. In the field effect transistor of the present invention, a source junction and a drain junction are thin, and the overlap between the source and the gate and between the drain and the gate is prevented, thereby lowering parasitic resistance. Further, the gate electric field is easily introduced to the drain extending region, so that the carrier concentration is effectively controlled in the channel at the drain. Also, the drain extending region is formed to be thinner than the source, so that the short channel characteristic is excellent.
摘要翻译：提供一种场效应晶体管及其制造方法，其中通过采用用于形成侧壁间隔物的技术和调节薄膜的沉积厚度，形成具有超精细沟道长度的场效应晶体管。在本发明的场效应晶体管中，源极结和漏极结很薄，并且防止源极和栅极之间以及漏极和栅极之间的重叠，从而降低寄生电阻。此外，栅极电场容易地被引入到漏极延伸区域，使得在漏极的沟道中有效地控制载流子浓度。此外，漏极延伸区域形成为比源极薄，使得短沟道特性优异。

3. 发明授权

US5981993A Flash memory device and method of fabricating the same 失效
标题翻译：闪存装置及其制造方法
公开(公告)号：US5981993A
公开(公告)日：1999-11-09
申请号：US965232
申请日：1997-11-06
申请人： Won-Ju Cho
发明人： Won-Ju Cho
IPC分类号： H01L21/28 , H01L21/768 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792 , H01L29/72
CPC分类号： H01L21/28273 , H01L29/42324
摘要： A semiconductor memory device and method of fabricating the same includes a first insulation layer and a first conductive layer formed on a substrate; conductive sidewall spacers protruding upwardly on the sides of the first conductive layer; a second insulation layer formed on the substrate and covering the conductive sidewall spacers; a second conductive layer, a third insulation layer, a third conductive layer, and a fourth insulation layer sequentially formed on the second insulation layer; a contact hole formed through the second and third conductive layers and the second through fourth insulation layers; insulative sidewall spacers formed on the sidewalls of the contact hole; and a fourth conductive layer formed in the contact hole so as to be in contact with the first conductive layer. The gate structure of the semiconductor memory device effectively prevents electrons from tunneling from the fourth conductive layer (data line) to the third conductive layer (control gate) through the inter-layer insulation layer formed on the second conductive layer (floating gate) by providing a strong electrical field at the upper tips of the conductive sidewall spacers, though a low voltage is applied to the gate electrode of the semiconductor memory device.
摘要翻译：半导体存储器件及其制造方法包括形成在衬底上的第一绝缘层和第一导电层; 在第一导电层的侧面向上突出的导电侧壁隔离物; 形成在所述基板上并覆盖所述导电侧壁间隔物的第二绝缘层; 第二导电层，第三绝缘层，第三导电层和顺序地形成在第二绝缘层上的第四绝缘层; 形成穿过第二和第三导电层和第二至第四绝缘层的接触孔; 形成在接触孔的侧壁上的绝缘侧壁间隔物; 以及形成在所述接触孔中以与所述第一导电层接触的第四导电层。半导体存储器件的栅极结构通过提供形成在第二导电层（浮栅）上的层间绝缘层，有效地防止电子从第四导电层（数据线）到第三导电层（控制栅极）的隧穿尽管在半导体存储器件的栅电极施加了低电压，但是在导电侧壁间隔物的上端处的强电场。

4. 发明授权

US5849619A Method for formation of capacitors 失效
标题翻译：电容器形成方法
公开(公告)号：US5849619A
公开(公告)日：1998-12-15
申请号：US769627
申请日：1996-12-18
申请人： Won-Ju Cho , Wouns Yang
发明人： Won-Ju Cho , Wouns Yang
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/108 , H01L21/20
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/91
摘要： A method of forming a capacitor for a DRAM includes the steps of: forming an insulating layer with a contact hole on a substrate; forming a first conductive layer on the insulating layer and in the contact hole; forming a temporary layer pattern on a portion of the first conductive layer corresponding to the contact hole; forming a second conductive layer on the first conductive layer and on the temporary layer pattern; selectively implanting oxygen ions into the first and second conductive layers except a portion of the second conductive layer corresponding to a side face of the temporary layer pattern; heat treating so as to convert the oxygen-ion-implanted first and second conductive layer portions into an oxide; removing the oxide and temporary layer pattern; forming a dielectric layer on the surface of the first and second conductive layers; and forming a third conductive layer on the dielectric layer.
摘要翻译：形成用于DRAM的电容器的方法包括以下步骤：在衬底上形成具有接触孔的绝缘层; 在绝缘层和接触孔中形成第一导电层; 在对应于接触孔的第一导电层的一部分上形成临时层图案; 在所述第一导电层和所述临时层图案上形成第二导电层; 除了对应于临时层图案的侧面的第二导电层的一部分之外，有选择地将氧离子注入到第一和第二导电层中; 热处理以将注入氧离子的第一和第二导电层部分转化为氧化物; 去除氧化物和临时层图案; 在所述第一和第二导电层的表面上形成介电层; 以及在所述电介质层上形成第三导电层。

5. 发明授权

US06723587B2 Ultra small-sized SOI MOSFET and method of fabricating the same 有权
标题翻译：超小型SOI MOSFET及其制造方法
公开(公告)号：US06723587B2
公开(公告)日：2004-04-20
申请号：US10331568
申请日：2002-12-31
申请人： Won-Ju Cho , Jong-Heon Yang , Moon-Gyu Jang , Seong-Jae Lee , Kyoung-Wan Park , Ki-Ju Im , Ji-Hun Oh
发明人： Won-Ju Cho , Jong-Heon Yang , Moon-Gyu Jang , Seong-Jae Lee , Kyoung-Wan Park , Ki-Ju Im , Ji-Hun Oh
IPC分类号： H01L2184
CPC分类号： H01L29/78696 , H01L29/66772 , H01L29/78609
摘要： An ultra small-sized SOI MOSFET having a high integration density, low power consumption, but high performances, and a method of fabricating the same are provided. The method includes preparing a SOI substrate on which a monocrystalline silicon layer is formed, forming a first dielectric material layer doped with impurities of a first conductivity type on the SOI substrate, forming an opening to expose the monocrystalline silicon layer etching at least part of the first dielectric material layer, forming a channel region injecting impurities of a second conductivity type into the monocrystalline silicon layer exposed by the opening, forming a source region and a drain region in the monocrystalline silicon layer diffusing the impurities of the first dielectric material layer using heat treatment, forming a gate dielectric layer in the opening on the channel region, forming a gate electrode on the gate dielectric layer to fit in the opening, forming a second dielectric material layer on the entire surface of the SOI substrate on which the gate electrode is formed, forming contact holes to expose the gate electrode, the source region, and the drain region etching part of the second dielectric material layer, and forming metal interconnections to bury the contact holes.
摘要翻译：提供了具有高积分密度，低功耗但高性能的超小尺寸SOI MOSFET及其制造方法。该方法包括制备在其上形成单晶硅层的SOI衬底，在SOI衬底上形成掺杂有第一导电类型的杂质的第一介电材料层，形成开口，以暴露单晶硅层，刻蚀至少部分第一介电材料层，形成将由第二导电类型杂质注入由开口露出的单晶硅层的沟道区，在单晶硅层中形成源极区和漏极区，使用热量扩散第一介电材料层的杂质在沟道区域的开口中形成栅极电介质层，在栅极电介质层上形成栅电极以配合在开口中，在栅极电极的SOI衬底的整个表面上形成第二电介质层形成，形成接触孔以露出栅电极，源极区和漏极区域蚀刻第二介电材料层的部分，以及形成用于埋入接触孔的金属互连。

6. 发明授权

US5840601A Thin film transistor and method for making same 失效
标题翻译：薄膜晶体管及其制造方法
公开(公告)号：US5840601A
公开(公告)日：1998-11-24
申请号：US773593
申请日：1996-12-27
申请人： Won-Ju Cho
发明人： Won-Ju Cho
IPC分类号： H01L21/336 , H01L21/8244 , H01L27/11 , H01L29/786 , H01L21/84
CPC分类号： H01L29/66765 , H01L29/78645
摘要： A thin film transistor and method include a substrate and a first insulating layer having a trench portion. A first gate is formed on the first insulating layer and a second insulating layer is formed on the first gate. An active layer is formed on the second gate insulating layer and a third insulating layer is formed on the active layer. The second and third insulating layers include a contact hole. A second gate is formed on the third insulating layer and is connected to the first gate through the contact hole.
摘要翻译：薄膜晶体管和方法包括衬底和具有沟槽部分的第一绝缘层。第一栅极形成在第一绝缘层上，第二绝缘层形成在第一栅极上。在第二栅绝缘层上形成有源层，在有源层上形成第三绝缘层。第二绝缘层和第三绝缘层包括接触孔。第二栅极形成在第三绝缘层上，并通过接触孔连接到第一栅极。

7. 发明授权

US5753544A Crystallization process and method of manufacturing thin film transistor using same 失效
标题翻译：使用其制造薄膜晶体管的结晶工艺和方法
公开(公告)号：US5753544A
公开(公告)日：1998-05-19
申请号：US499255
申请日：1995-07-07
申请人： Won Ju Cho , Jae Sung Roh
发明人： Won Ju Cho , Jae Sung Roh
IPC分类号： H01L21/20 , H01L21/336 , H01L29/786 , H01L21/00
CPC分类号： H01L29/66757 , H01L21/2022 , H01L29/66765 , H01L29/78654 , H01L29/78675 , H01L29/78678
摘要： A crystallization process comprising the steps of depositing a polycrystalline silicon layer on a semiconductor substrate, implanting silicon ions into first and second areas of the polycrystalline silicon layer in different amounts such that crystals having a predetermined plane direction remain in the second area and such that the first area becomes amorphous, and performing a thermal treatment to recrystallize the amorphous second area using the crystals having the predetermined plane direction remaining in the first area as a nucleus.
摘要翻译：一种结晶方法，包括以下步骤：在半导体衬底上沉积多晶硅层，以不同的量将硅离子注入多晶硅层的第一和第二区域，使得具有预定平面方向的晶体保留在第二区域中，第一区域变为无定形，并且使用具有保留在第一区域中的预定平面方向的晶体作为核，进行热处理以使无定形第二区域再结晶。

8. 发明申请

US20060079057A1 Field effect transistor and method of fabricating the same 有权
公开(公告)号：US20060079057A1
公开(公告)日：2006-04-13
申请号：US11125101
申请日：2005-05-10
申请人： Won-ju Cho , Chang-geun Ahn , Ki-ju Im , Jong-heon Yang , In-bok Baek , Seong-jae Lee
发明人： Won-ju Cho , Chang-geun Ahn , Ki-ju Im , Jong-heon Yang , In-bok Baek , Seong-jae Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/7835 , H01L29/41783 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/66659 , H01L29/7834
摘要： Provided are a field effect transistor and a method of fabricating the same, wherein the field effect transistor is formed which has a hyperfine channel length by employing a technique for forming a sidewall spacer and adjusting the deposition thickness of a thin film. In the field effect transistor of the present invention, a source junction and a drain junction are thin, and the overlap between the source and the gate and between the drain and the gate is prevented, thereby lowering parasitic resistance. Further, the gate electric field is easily introduced to the drain extending region, so that the carrier concentration is effectively controlled in the channel at the drain. Also, the drain extending region is formed to be thinner than the source, so that the short channel characteristic is excellent.

9. 发明授权

US06797629B2 Method of manufacturing nano transistors 失效
标题翻译：制造纳米晶体管的方法
公开(公告)号：US06797629B2
公开(公告)日：2004-09-28
申请号：US10185104
申请日：2002-06-27
申请人： Moon Gyu Jang , Won Ju Cho , Seong Jae Lee , Kyoung Wan Park
发明人： Moon Gyu Jang , Won Ju Cho , Seong Jae Lee , Kyoung Wan Park
IPC分类号： H01L21302
CPC分类号： H01L29/78648 , H01L21/84 , H01L27/1203 , H01L29/78654
摘要： The present invention relates to a method of manufacturing a nano transistor. The present invention manufactures the nano transistor without changing a conventional method of forming the nano transistor formed on a SOI substrate. Further, the present invention includes forming a N well and a P well at giving regions of an underlying silicon substrate so that a given voltage can be individually applied to a NMOS transistor and a PMOS transistor. Therefore, the present invention can control the threshold voltage to prevent an increase of the leakage current.
摘要翻译：本发明涉及纳米晶体管的制造方法。本发明制造纳米晶体管而不改变形成在SOI衬底上的纳米晶体管的常规方法。此外，本发明包括在给定下面的硅衬底的区域上形成N阱和P阱，使得可以将给定的电压单独地施加到NMOS晶体管和PMOS晶体管。因此，本发明可以控制阈值电压以防止漏电流的增加。

10. 发明授权

US6143669A Method of growing gate oxides 有权
标题翻译：生长栅极氧化物的方法
公开(公告)号：US6143669A
公开(公告)日：2000-11-07
申请号：US192498
申请日：1998-11-17
申请人： Won Ju Cho
发明人： Won Ju Cho
IPC分类号： H01L29/78 , H01L21/334 , H01L21/8234 , H01L27/088 , H01L21/31
CPC分类号： H01L21/823462
摘要： A method for manufacturing a gate oxide film in a semiconductor device includes: preparing a semiconductor substrate having a first and a second active region; implanting germanium ions into the first active region; and forming a first and a second gate oxide films on the first and the second active regions, respectively, wherein the first gate oxide film is thicker than the second gate oxide film.
摘要翻译：一种在半导体器件中制造栅极氧化膜的方法，包括：制备具有第一和第二有源区的半导体衬底; 将锗离子注入第一活性区; 以及分别在所述第一和第二有源区上形成第一和第二栅极氧化膜，其中所述第一栅极氧化物膜比所述第二栅极氧化物膜厚。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式