专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20060079057A1 Field effect transistor and method of fabricating the same 有权
公开(公告)号：US20060079057A1
公开(公告)日：2006-04-13
申请号：US11125101
申请日：2005-05-10
申请人： Won-ju Cho , Chang-geun Ahn , Ki-ju Im , Jong-heon Yang , In-bok Baek , Seong-jae Lee
发明人： Won-ju Cho , Chang-geun Ahn , Ki-ju Im , Jong-heon Yang , In-bok Baek , Seong-jae Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/7835 , H01L29/41783 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/66659 , H01L29/7834
摘要： Provided are a field effect transistor and a method of fabricating the same, wherein the field effect transistor is formed which has a hyperfine channel length by employing a technique for forming a sidewall spacer and adjusting the deposition thickness of a thin film. In the field effect transistor of the present invention, a source junction and a drain junction are thin, and the overlap between the source and the gate and between the drain and the gate is prevented, thereby lowering parasitic resistance. Further, the gate electric field is easily introduced to the drain extending region, so that the carrier concentration is effectively controlled in the channel at the drain. Also, the drain extending region is formed to be thinner than the source, so that the short channel characteristic is excellent.

2. 发明授权

US07750378B2 Field effect transistor and method of fabricating the same 有权
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US07750378B2
公开(公告)日：2010-07-06
申请号：US11400520
申请日：2006-04-10
申请人： Won-ju Cho , Chang-geun Ahn , Ki-ju Im , Jong-heon Yang , In-bok Baek , Seong-jae Lee
发明人： Won-ju Cho , Chang-geun Ahn , Ki-ju Im , Jong-heon Yang , In-bok Baek , Seong-jae Lee
IPC分类号： H01L29/78
CPC分类号： H01L29/7835 , H01L29/41783 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/66659 , H01L29/7834
摘要： Provided are a field effect transistor and a method of fabricating the same, wherein the field effect transistor is formed which has a hyperfine channel length by employing a technique for forming a sidewall spacer and adjusting the deposition thickness of a thin film. In the field effect transistor of the present invention, a source junction and a drain junction are thin, and the overlap between the source and the gate and between the drain and the gate is prevented, thereby lowering parasitic resistance. Further, the gate electric field is easily introduced to the drain extending region, so that the carrier concentration is effectively controlled in the channel at the drain. Also, the drain extending region is formed to be thinner than the source, so that the short channel characteristic is excellent.
摘要翻译：提供一种场效应晶体管及其制造方法，其中通过采用用于形成侧壁间隔物的技术和调节薄膜的沉积厚度，形成具有超精细沟道长度的场效应晶体管。在本发明的场效应晶体管中，源极结和漏极结很薄，并且防止源极和栅极之间以及漏极和栅极之间的重叠，从而降低寄生电阻。此外，栅极电场容易地被引入到漏极延伸区域，使得在漏极的沟道中有效地控制载流子浓度。此外，漏极延伸区域形成为比源极薄，使得短沟道特性优异。

3. 发明授权

US07060580B2 Field effect transistor and method of fabricating the same 有权
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US07060580B2
公开(公告)日：2006-06-13
申请号：US11125101
申请日：2005-05-10
申请人： Won-ju Cho , Chang-geun Ahn , Ki-ju Im , Jong-heon Yang , In-bok Baek , Seong-jae Lee
发明人： Won-ju Cho , Chang-geun Ahn , Ki-ju Im , Jong-heon Yang , In-bok Baek , Seong-jae Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/7835 , H01L29/41783 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/66659 , H01L29/7834
摘要： Provided are a field effect transistor and a method of fabricating the same, wherein the field effect transistor is formed which has a hyperfine channel length by employing a technique for forming a sidewall spacer and adjusting the deposition thickness of a thin film. In the field effect transistor of the present invention, a source junction and a drain junction are thin, and the overlap between the source and the gate and between the drain and the gate is prevented, thereby lowering parasitic resistance. Further, the gate electric field is easily introduced to the drain extending region, so that the carrier concentration is effectively controlled in the channel at the drain. Also, the drain extending region is formed to be thinner than the source, so that the short channel characteristic is excellent.
摘要翻译：提供一种场效应晶体管及其制造方法，其中通过采用用于形成侧壁间隔物的技术和调节薄膜的沉积厚度，形成具有超精细沟道长度的场效应晶体管。在本发明的场效应晶体管中，源极结和漏极结很薄，并且防止源极和栅极之间以及漏极和栅极之间的重叠，从而降低寄生电阻。此外，栅极电场容易地被引入到漏极延伸区域，使得在漏极的沟道中有效地控制载流子浓度。此外，漏极延伸区域形成为比源极薄，使得短沟道特性优异。

4. 发明申请

US20060180867A1 Field effect transistor and method of fabricating the same 有权
公开(公告)号：US20060180867A1
公开(公告)日：2006-08-17
申请号：US11400520
申请日：2006-04-10
申请人： Won-ju Cho , Chang-geun Ahn , Ki-ju Im , Jong-heon Yang , In-bok Baek , Seong-jae Lee
发明人： Won-ju Cho , Chang-geun Ahn , Ki-ju Im , Jong-heon Yang , In-bok Baek , Seong-jae Lee
IPC分类号： H01L21/336 , H01L29/94
CPC分类号： H01L29/7835 , H01L29/41783 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/66659 , H01L29/7834
摘要： Provided are a field effect transistor and a method of fabricating the same, wherein the field effect transistor is formed which has a hyperfine channel length by employing a technique for forming a sidewall spacer and adjusting the deposition thickness of a thin film. In the field effect transistor of the present invention, a source junction and a drain junction are thin, and the overlap between the source and the gate and between the drain and the gate is prevented, thereby lowering parasitic resistance. Further, the gate electric field is easily introduced to the drain extending region, so that the carrier concentration is effectively controlled in the channel at the drain. Also, the drain extending region is formed to be thinner than the source, so that the short channel characteristic is excellent.

5. 发明授权

US06620668B2 Method of fabricating MOS transistor having shallow source/drain junction regions 失效
标题翻译：制造具有浅源极/漏极结区域的MOS晶体管的方法
公开(公告)号：US06620668B2
公开(公告)日：2003-09-16
申请号：US10117001
申请日：2002-04-05
申请人： Seong-jae Lee , Won-ju Cho , Kyoung-wan Park
发明人： Seong-jae Lee , Won-ju Cho , Kyoung-wan Park
IPC分类号： H01L218238
CPC分类号： H01L29/6659 , H01L21/2255 , H01L21/26586 , H01L21/823814 , H01L29/7833
摘要： A method of fabricating a MOS transistor having shallow source/drain junction regions is provided. A diffusion source layer is formed on a semiconductor substrate on which gate patterns are formed. Same type or different type of impurities are implanted into the diffusion source layer several times in different directions. As a result, dislocation does not occur and the impurity concentration of the diffusion source layer can be nonuniformly controlled so that damage to the crystal structure of the semiconductor substrate does not occur. Also, the impurities nonuniformly contained in the diffusion source layer are diffused into the semiconductor substrate by a solid phase diffusion method to form shallow source/drain junction regions having LDD regions and highly doped source/drain regions by a self-alignment method.
摘要翻译：提供一种制造具有浅源极/漏极结区域的MOS晶体管的方法。扩散源层形成在其上形成有栅极图案的半导体衬底上。相同类型或不同类型的杂质在不同方向上多次注入扩散源层。结果，不会发生位错，扩散源层的杂质浓度可能被不均匀地控制，从而不会发生对半导体衬底的晶体结构的损坏。此外，扩散源层中不均匀地包含的杂质通过固相扩散法扩散到半导体衬底中，以通过自对准方法形成具有LDD区和高掺杂源极/漏极区的浅源极/漏极结区域。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式