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    • 2. 发明授权
    • Low offset automatic frequency tuning circuits for continuous-time filter
    • 低偏移自动频率调谐电路,用于连续时间滤波
    • US06400932B1
    • 2002-06-04
    • US09454389
    • 1999-12-03
    • Chang Jun OhJong Kee KwonJong Ryul LeeWon Chul SongHee Bum JungKyung Soo KimHan Jin ChoOok Kim
    • Chang Jun OhJong Kee KwonJong Ryul LeeWon Chul SongHee Bum JungKyung Soo KimHan Jin ChoOok Kim
    • H04B118
    • H03H11/0422H03L7/06
    • The present invention relates to a tuning circuit, more specifically to a tuning circuit for continuous-time filter capable of making exact the Gm value to minimize the variation of the cutoff frequency due to the variation of process in the Gm-C type of continuous-time filter. According to the invention, a frequency tuning circuit is provided which comprises integrating means for generating a signal discharging from a first reference voltage to a first predetermined value and a signal charging from a second reference voltage to a second predetermined value; offset sampling means for sampling the offset voltages of the Gm cells by receiving a current multiplied by the offset voltages from the Gm cells included in the integrating means and providing a feedback path between the output nodes and the input nodes of the included Gm cells; comparative signal generating means for generating a comparative signal by generating a reference signal by dividing a clock inputted from the external, receiving the signal discharging from the first reference voltage to the first predetermined value and the signal charging from the second reference voltage to the second predetermined value from the integrating means, and comparing the actual intersection and the target intersection of these signals; and control means for generating a control signal to regulate the Gm values of the integrating means and the offset sampling means by receiving the reference signal and the comparative signal from the comparative signal generating means and detecting the phase differences therebetween.
    • 调谐电路技术领域本发明涉及一种调谐电路,更具体地说涉及一种用于连续时间滤波器的调谐电路,其能够精确地确定Gm值,以使由于Gm-C型连续时间滤波器中的工艺变化引起的截止频率的变化最小化, 时间过滤器。 根据本发明,提供了一种频率调谐电路,其包括用于产生从第一参考电压放电到第一预定值的信号的积分装置和从第二参考电压到第二预定值的信号充电; 偏移采样装置,用于通过接收与积分装置中包括的Gm单元的偏移电压相乘的电流来对Gm单元的偏移电压进行采样,并在输出节点和所包括的Gm单元的输入节点之间提供反馈路径; 比较信号发生装置,用于通过将从外部输入的时钟分频,将从第一参考电压放电的信号接收到第一预定值和从第二参考电压到第二预定值的信号充电来产生参考信号, 从积分装置获取值,并比较这些信号的实际交点和目标交点; 以及控制装置,用于通过从比较信号发生装置接收参考信号和比较信号并检测它们之间的相位差,产生控制信号以调节积分装置和偏移采样装置的Gm值。
    • 3. 发明授权
    • CMOS variable gain amplifier and control method therefor
    • CMOS可变增益放大器及其控制方法
    • US06259321B1
    • 2001-07-10
    • US09490732
    • 2000-01-25
    • Won Chul SongChang Jun OhHee Bum Jung
    • Won Chul SongChang Jun OhHee Bum Jung
    • H03F345
    • H03G1/0029H03F3/45188H03F2203/45458H03F2203/45702
    • A CMOS high frequency variable gain amplifier with maximum high frequency operation and wide variable gain characteristics that is formed from an amplifier having a plurality of variable gain amplifier cells connected in series for continuously enabling wide gain variation; and a control voltage generator for generating and outputting the control voltage of the variable gain amplifier cells. By using both the saturation region and the linear region of input differential transistors constituting the variable gain amplifier cells in order to obtain wide gain variation characteristics, it is possible for the variable gain amplifier to operate in the saturation region when the input signal is small to obtain a high gain and to operate in the linear region when the input signal is large to obtain minimum distortion and a low gain. Also, it is possible for the gain to have the characteristics in the form of an exponential function to the gain control voltage.
    • 具有最大高频运算和宽可变增益特性的CMOS高频可变增益放大器,其由具有串联连接的多个可变增益放大器单元的放大器形成,以连续实现宽增益变化; 以及用于产生和输出可变增益放大器单元的控制电压的控制电压发生器。 通过使用构成可变增益放大器单元的输入差分晶体管的饱和区域和线性区域,为了获得宽的增益变化特性,当输入信号小到等于可变增益放大器时,可以在饱和区域中工作 获得高增益并且在输入信号大时在线性区域中操作以获得最小失真和低增益。 此外,增益可以具有对增益控制电压的指数函数形式的特性。
    • 7. 发明授权
    • Low pass filter
    • 低通滤波器
    • US6091289A
    • 2000-07-18
    • US99388
    • 1998-06-18
    • Won Chul SongJong Ryul LeeChang Jun OhJong Kee KwonOok KimKyung Soo Kim
    • Won Chul SongJong Ryul LeeChang Jun OhJong Kee KwonOok KimKyung Soo Kim
    • H03H9/46H03H11/04H03K5/00
    • H03H11/04
    • There is disclosed a low frequency filter. A low frequency cutoff filter includes a filter circuit having a capacitor connected between an input terminal and an output terminal and an active resistor connected to the output terminal, having a very large resistance, and a bias circuit having a negative feedback to set a biasing voltage of the active resistor to a desired value, thereby implementing the cutoff filter within a semiconductor chip as one set with the capacitor having a small capacitance. A low frequency pass filter includes an active resistor having a very large resistance, means for setting a biasing voltage of the active resistor to a desired value, and a capacitor connected between the output terminal and the ground. Therefore, the low pass filter can be integrated-circuited using even small capacitor.
    • 公开了一种低频滤波器。 低频截止滤波器包括滤波器电路,其具有连接在输入端子和输出端子之间的电容器和连接到具有非常大电阻的输出端子的有源电阻器,以及具有负反馈以设置偏置电压的偏置电路 将所述有源电阻器设置为期望值,从而在半导体芯片内实现截止滤波器作为一组,其中电容器具有小电容。 低通滤波器包括具有非常大电阻的有源电阻器,用于将有源电阻器的偏置电压设置为期望值的装置,以及连接在输出端子和地之间的电容器。 因此,低通滤波器可以使用甚至小的电容器集成。
    • 9. 发明授权
    • Integrated circuit built-in type supply power delay circuit
    • 集成电路内置式电源延时电路
    • US5886550A
    • 1999-03-23
    • US877408
    • 1997-06-16
    • Jong-Kee KwonGyu-Dong KimOok KimChang-Jun OhJong-Ryul LeeWon-Chul SongKyung-Soo Kim
    • Jong-Kee KwonGyu-Dong KimOok KimChang-Jun OhJong-Ryul LeeWon-Chul SongKyung-Soo Kim
    • G11C5/14H03K17/22
    • H03K17/223
    • An integrated circuit built-in type power delay circuit which is capable of supplying a stable supply power to each circuit of the integrated circuit by generating a supply power control signal voltage after a predetermined time. The circuit includes a receiving unit for receiving a supply voltage VDD and charging the same, a supplying unit for supplying a current, an inverting unit for inverting an output value from the charging unit, a switching unit controlled in accordance with an output value from the inverting unit for switching an output from the current supply unit, a current regenerating unit for receiving a control of the switching unit and discharging an output value from the charging unit, an electric potential value conversion unit controlled by an output value from the inverting unit for converting an output value from the charging unit into a low level, and a buffering unit for receiving an output value from the inverting unit for buffering the output value and outputting a non-inverted signal.
    • 一种集成电路内置型功率延迟电路,其能够通过在预定时间之后产生电源功率控制信号电压来向集成电路的每个电路提供稳定的供电。 该电路包括:接收单元,用于接收电源电压VDD并对其进行充电;提供单元,用于提供电流;反相单元,用于反转来自充电单元的输出值;开关单元,根据来自 用于切换来自电流供应单元的输出的反相单元,用于接收开关单元的控制并从充电单元放电输出值的电流再生单元,由来自反相单元的输出值控制的电位值转换单元, 将来自充电单元的输出值转换为低电平;以及缓冲单元,用于从反相单元接收输出值,用于缓冲输出值并输出非反相信号。