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1. 发明授权

US4620299A Row decoder 失效
标题翻译：行解码器
公开(公告)号：US4620299A
公开(公告)日：1986-10-28
申请号：US709262
申请日：1985-03-04
申请人： Scott Remington , William L. Martino, Jr.
发明人： Scott Remington , William L. Martino, Jr.
IPC分类号： G11C8/10 , G11C8/00 , G11C7/02
CPC分类号： G11C8/10
摘要： A logic decoder provides a true output signal at a first logic state when selected during an active cycle and during an inactive cycle, and at a second logic state when deselected. The logic decoder also provides a complementary output signal. A word line driver circuit couples decoded address signals to respective word lines when the output signal is in the first logic state. A coupling circuit couples one of first and second word lines to ground during the active cycle. A coupling transistor couples the first and second word lines together in response to receiving the complementary output signal at the first logic state.
摘要翻译：逻辑解码器在主动周期期间和非活动周期期间选择时以第一逻辑状态提供真实输出信号，并且在取消选择时处于第二逻辑状态。逻辑解码器还提供互补的输出信号。当输出信号处于第一逻辑状态时，字线驱动器电路将解码的地址信号耦合到相应的字线。在活动周期期间，耦合电路将第一和第二字线中的一个耦合到地。响应于在第一逻辑状态接收到互补输出信号，耦合晶体管将第一和第二字线耦合在一起。

2. 发明授权

US4401897A Substrate bias voltage regulator 失效
标题翻译：基板偏置电压调节器
公开(公告)号：US4401897A
公开(公告)日：1983-08-30
申请号：US244832
申请日：1981-03-17
申请人： William L. Martino, Jr. , Jerry D. Moench
发明人： William L. Martino, Jr. , Jerry D. Moench
IPC分类号： G05F3/20 , H03L5/00 , H03K17/693
CPC分类号： G05F3/205
摘要： A substrate bias voltage regulator selectively provides one of two predetermined substrate bias voltage levels in response to a timing signal. The selection of substrate bias voltage level is achieved via a reference generator circuit which provides one of two predetermined reference voltages to a control circuit which regulates the substrate bias voltage to the selected level.
摘要翻译：衬底偏置电压调节器响应于定时信号选择性地提供两个预定衬底偏置电压电平中的一个。通过参考发生器电路来实现衬底偏置电压电平的选择，该参考发生器电路将两个预定参考电压之一提供给将衬底偏置电压调节到所选电平的控制电路。

3. 发明授权

US4291246A Differential capacitive buffer 失效
标题翻译：差分电容缓冲器
公开(公告)号：US4291246A
公开(公告)日：1981-09-22
申请号：US17524
申请日：1979-03-05
申请人： William L. Martino, Jr. , Jerry D. Moench
发明人： William L. Martino, Jr. , Jerry D. Moench
IPC分类号： H03K3/356 , H03K5/01 , G11C8/00 , H03K17/30
CPC分类号： H03K3/356026
摘要： A balanced differential circuit is provided which is useful as an address buffer in digital memories. The circuit is illustrated as a single ended input circuit having complementary outputs. Capacitors are used to couple imbalancing signals into the circuit. Through selective timing of load devices within the circuit power dissipation is kept to a minimum.
摘要翻译：提供了一种平衡差分电路，可用作数字存储器中的地址缓冲器。该电路被示为具有互补输出的单端输入电路。电容器用于将不平衡信号耦合到电路中。通过电路内的负载设备的选择性定时功耗最小化。

4. 发明授权

US4979145A Structure and method for improving high speed data rate in a DRAM 失效
标题翻译：用于提高DRAM中的高速数据速率的结构和方法
公开(公告)号：US4979145A
公开(公告)日：1990-12-18
申请号：US858326
申请日：1986-05-01
申请人： Scott Remington , William L. Martino, Jr.
发明人： Scott Remington , William L. Martino, Jr.
IPC分类号： G11C7/00 , G11C7/10 , G11C7/14 , G11C8/18
CPC分类号： G11C7/14 , G11C7/00 , G11C7/1006 , G11C7/1015 , G11C8/18
摘要： A dynamic random access memory has a bit of data selected by a multiplexed address. The row address latches twice as much data as can be selected by the column address which follows the row address. After the column address has been utilized, there is still a one of two selection between two bits of data required. One of the row addresses provides the final selection between the two bits of data. An array toggle signal available from an extra pin is used to switch the state of the internal signal which corresponds to the one row address signal which makes the final one of two selection. The array toggle signal thus makes it possible to access any of the latched data in a high speed mode in which only the column address is changed to select among the bits of data which are already latched.
摘要翻译：动态随机存取存储器具有通过多路复用地址选择的数据位。行地址锁存的数据是可以通过行地址后面的列地址选择的数据量的两倍。在列地址被使用之后，仍然需要两位数据之间的两个选择之一。行地址之一提供了两位数据之间的最终选择。可以使用从额外引脚提供的阵列跳变信号来切换对应于一行地址信号的内部信号的状态，这是两个选择中的最后一个。因此，阵列触发信号使得可以在只有列地址被改变以选择已被锁存的数据位之中的高速模式中访问任何锁存数据。

5. 发明授权

US4661724A Row decoder 失效
标题翻译：行解码器
公开(公告)号：US4661724A
公开(公告)日：1987-04-28
申请号：US731199
申请日：1985-05-06
申请人： Scott Remington , William L. Martino, Jr.
发明人： Scott Remington , William L. Martino, Jr.
IPC分类号： G11C8/10 , H03M7/22 , H03K19/094 , G11C8/00 , H03K17/16 , H03K19/20
CPC分类号： H03M7/22 , G11C8/10
摘要： A row decoder includes a logic decoder, a word line driver circuit, and first and second coupling circuits. The logic decoder provides a logic high in an inactive cycle and when selected in an active cycle, and a logic low when deselected in the active cycle. Each of a plurality of word line driver circuits receive a decoded address signal which corresponds to that particular driver circuit, each have an output coupled to a corresponding word line, and each have an input which, when at a logic high, causes that word line driver to couple its corresponding decoded address signal to its corresponding word line. The first coupling circuit couples the output of the logic decoder to the input of only the driver circuit which corresponds to an active decoded address signal during the active cycle, and for coupling the output of the logic decoder to all of the driver circuits in the inactive cycle. The second coupling circuit couples the word line which corresponds to the active decoded signal to the output of the logic decoder when the logic decoder is deselected during the active cycle.
摘要翻译：行解码器包括逻辑解码器，字线驱动电路以及第一和第二耦合电路。逻辑解码器在非活动周期中提供逻辑高电平，并在激活周期内选择逻辑电平，当在激活周期中取消选择时，该逻辑电路提供逻辑低电平。多个字线驱动器电路中的每一个接收与该特定驱动器电路相对应的解码的地址信号，每个具有耦合到对应的字线的输出，并且每个具有输入，当逻辑高时，该输入使该字线驱动器将其对应的解码的地址信号耦合到其对应的字线。第一耦合电路将逻辑解码器的输出耦合到仅在激活周期期间对应于有源解码地址信号的驱动器电路的输入，并且将逻辑解码器的输出耦合到不活动的所有驱动器电路周期。当在活动周期期间取消选择逻辑解码器时，第二耦合电路将对应于有效解码信号的字线耦合到逻辑解码器的输出端。

6. 发明授权

US4110840A Sense line charging system for random access memory 失效
标题翻译：用于随机存取存储器的感应线充电系统
公开(公告)号：US4110840A
公开(公告)日：1978-08-29
申请号：US753235
申请日：1976-12-22
申请人： Kichio Abe , William L. Martino, Jr.
发明人： Kichio Abe , William L. Martino, Jr.
IPC分类号： G11C11/412 , G11C11/419 , G11C7/00
CPC分类号： G11C11/419 , G11C11/412
摘要： A random access memory includes a column of static MOS storage cells. Two sense-write conductors are coupled to each cell in the column. Each sense-write conductor is also coupled, respectively, to a termination MOSFET. The first sense-write conductor of each column of storage cells is coupled by means of a first coupling MOSFET to a first bit-sense conductor. The second sense-write conductor of each column of storage cells is coupled, by a second MOSFET to a second bit-sense conductor. Each pair of sense-write conductors is coupled to a V.sub.DD conductor by a separate charging MOSFET having its gate electrode coupled to a circuit for generating a pulse at the end of a write cycle. Since at the end of any write operation, the two bit-sense conductors and the two sense-write conductors of the selected column will be at opposite voltage levels, the pulse very rapidly precharges the voltages of the two sense-write conductors and of the two bit-sense conductors to levels which ensure that the data stored in the storage cell next selected will not be destroyed as a result of the opposite voltage levels of the two bit-sense conductors acting to write an undesired state into the storage cell selected next. The read access time of the memory is reduced by the amount of time required by the termination MOSFETS to charge a sense-write conductor and a bit-sense conductor to a MOSFET threshold drop below V.sub.DD minus the time required for the charging MOSFETs to precharge the sense-write and bit-sense conductors.
摘要翻译：随机存取存储器包括一列静态MOS存储单元。两个读写导体耦合到列中的每个单元。每个读写导体也分别耦合到端接MOSFET。每列存储单元的第一读写导体通过第一耦合MOSFET耦合到第一位读出导体。每列存储单元的第二读写导体通过第二MOSFET耦合到第二位检测导体。每对感测写入导体通过单独的充电MOSFET耦合到VDD导体，其中其栅极耦合到用于在写周期结束时产生脉冲的电路。由于在任何写操作结束时，所选列的两个位读取导体和两个读写导体将处于相反的电压电平，所以脉冲非常快速地预充电两个读写导体和两个位检测导体的电平确保存储在下一个选择的存储单元中的数据将不会被破坏，因为两个位检测导体的相反电压电平用于将不期望的状态写入下一个选择的存储单元。存储器的读取访问时间减少了终端MOSFET将针对读写导体和位读取导体充电到低于VDD的MOSFET阈值下降所需的时间，减去充电MOSFET预充电所需的时间读写和位读导体。

7. 发明授权

US06185139B2 Circuit and method for enabling semiconductor device burn-in 有权
标题翻译：用于使半导体器件老化的电路和方法
公开(公告)号：US06185139B2
公开(公告)日：2001-02-06
申请号：US09481864
申请日：2000-01-12
申请人： Dimitris C. Pantelakis , William L. Martino, Jr. , Eric S. Powers
发明人： Dimitris C. Pantelakis , William L. Martino, Jr. , Eric S. Powers
IPC分类号： G11C2900
CPC分类号： G01R31/30 , G01R31/3004
摘要： An integrated circuit device includes low voltage internal circuitry and a first external pin which receives a first information signal. The first information signal provides operating information within a predetermined voltage range. The device includes a mode detector coupled to the first external pin. The mode detector provides a mode enable signal in response to the first information signal being at a voltage that is outside the predetermined voltage range. The device further includes a switchable regulator which provides a supply voltage to the low voltage internal circuitry to power the low voltage internal circuitry at a regulated voltage in a normal mode of the integrated circuit memory and at a higher voltage than the regulated voltage in response to the mode enable signal.
摘要翻译：集成电路装置包括低电压内部电路和接收第一信息信号的第一外部引脚。第一信息信号在预定电压范围内提供操作信息。该装置包括耦合到第一外部引脚的模式检测器。模式检测器响应于第一信息信号处于超出预定电压范围的电压而提供模式使能信号。该装置还包括可切换调节器，其向低压内部电路提供电源电压，以在集成电路存储器的正常模式下以稳定的电压对电压为低压内部电路，并且响应于模式使能信号。

8. 发明授权

US5777935A Memory device with fast write recovery and related write recovery method 失效
标题翻译：具有快速写入恢复和相关写入恢复方式的内存设备
公开(公告)号：US5777935A
公开(公告)日：1998-07-07
申请号：US815527
申请日：1997-03-12
申请人： Dimitris C. Pantelakis , William L. Martino, Jr. , Derrick Leach , Frank A. Miller , Wai T. Lau
发明人： Dimitris C. Pantelakis , William L. Martino, Jr. , Derrick Leach , Frank A. Miller , Wai T. Lau
IPC分类号： G11C11/41 , G11C7/10 , G11C7/12 , G11C7/00
CPC分类号： G11C7/1048 , G11C7/12
摘要： A memory (10) such as a current sensing static random access memory (SRAM) achieves fast write recovery through bit line loads and two additional mechanisms. First, an additional load (252) on shared data lines also becomes active to speed the write recovery process. Second, multiple columns (200, 202, 204) are connected to common data lines during write recovery so that a column written to during a write cycle may be again precharged in part by charge sharing using the charge stored in other columns. These two mechanisms allow fast write recovery with minimum column pitch and avoid the problems which would be encountered if the loads were placed on the write data line.
摘要翻译：诸如电流感测静态随机存取存储器（SRAM）的存储器（10）通过位线负载和两个附加机制实现快速写入恢复。首先，在共享数据线上的额外负载（252）也变得活跃，以加速写恢复过程。第二，在写入恢复期间，多个列（200,202,204）连接到公共数据线，使得在写入周期期间写入的列可以通过使用存储在其他列中的电荷的电荷共享来部分地再次进行预充电。这两种机制允许以最小列间距进行快速写入恢复，并避免如果将负载放置在写入数据线上时会遇到的问题。

9. 发明授权

US4628253A Clock signal test circuit 失效
标题翻译：时钟信号测试电路
公开(公告)号：US4628253A
公开(公告)日：1986-12-09
申请号：US595194
申请日：1984-03-30
申请人： Ruey J. Yu , William L. Martino, Jr.
发明人： Ruey J. Yu , William L. Martino, Jr.
IPC分类号： G01R31/316 , G06F1/04 , G06F11/00 , G01R15/12 , G01R31/08 , H03K5/13
CPC分类号： G06F11/0751 , G01R31/316 , G06F1/04 , G06F11/0754
摘要： An integrated circuit which has serially connected clock drivers for generating sequential clock signals further includes test circuitry for testing for the occurence of the clock signals. The test circuitry includes a current source for each of the sequential clock signals each of which is enabled upon receiving its associated clock signal. Consequently, the current sources are sequentially enabled until a clock signal fails to occur at which time no more clock signals occur so that no more current sources are enabled. The current sources are connected to a probe pad which is accessible external to the integrated circuit. Test apparatus for detecting the enabled current sources can be connected to the integrated circuit at the probe pad.
摘要翻译：具有用于产生顺序时钟信号的串联连接的时钟驱动器的集成电路还包括用于测试时钟信号发生的测试电路。测试电路包括用于每个顺序时钟信号的电流源，每个时钟信号在接收到其关联的时钟信号时能够被使能。因此，电流源依次被使能，直到时钟信号不能发生，在此时间不再出现时钟信号，使得不再有电流源被使能。电流源连接到在集成电路外部可访问的探针焊盘。用于检测使能的电流源的测试装置可以连接到探针焊盘处的集成电路。

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