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1. 发明申请

US20080224273A1 CHEMICAL OXIDE REMOVAL OF PLASMA DAMAGED SICOH LOW K DIELECTRICS 有权
标题翻译：化学氧化物去除等离子体损耗的SICOH低K电介质
公开(公告)号：US20080224273A1
公开(公告)日：2008-09-18
申请号：US12044245
申请日：2008-03-07
申请人： William G. AMERICA , Steven H. Johnston , Brian W. Messenger
发明人： William G. AMERICA , Steven H. Johnston , Brian W. Messenger
IPC分类号： H01L23/58
CPC分类号： H01L21/312 , H01L21/02063 , H01L21/02126 , H01L21/31633 , H01L21/76814
摘要： A structure and method for removing damages of a dual damascene structure after plasma etching. The method includes the use of sublimation processes to deposit reactive material onto the damaged regions and conditions to achieve a controlled removal of the damaged region. Furthermore a semiconductor structure includes a dual damascene structure that has been treated by the method.
摘要翻译：等离子蚀刻后去除双镶嵌结构损坏的结构和方法。该方法包括使用升华过程将反应性材料沉积在受损区域上并且实现受损区域的受控去除的条件。此外，半导体结构包括已经通过该方法处理的双镶嵌结构。

2. 发明授权

US06300160B1 Process for charge coupled image sensor with U-shaped gates 有权
标题翻译：具有U型门的电荷耦合图像传感器的工艺
公开(公告)号：US06300160B1
公开(公告)日：2001-10-09
申请号：US09443271
申请日：1999-11-18
申请人： William G. America , David L. Losee
发明人： William G. America , David L. Losee
IPC分类号： H01L21339
CPC分类号： H01L27/14812
摘要： A method and apparatus of forming adjacent, non-overlapping CCD electrodes within an image sensing device such the electrodes are U-shaped. The device provided by the disclosed method employs a substrate with a gate dielectric layer formed on a surface of the substrate with a plurality of phases created within the CCD. A deposited silicon layer is placed on the surface of the CCD and a mask is used to cover areas other than the first set of electrodes. Etching takes places leaving the mask areas to the deposited silicon and a set of side walls to the remaining deposited silicon are then oxidized. A first set of electrodes by forming an electrode layer placed over the CCD. CMP is employed to remove remaining deposited silicon layer as well as portions of the electrode layer such that the side walls remain vertical portions to electrode layer remaining in the side walls. The process is then repeated by placing another electrode material layer and another CMP process leaving two sets of adjacent U-shaped gates.
摘要翻译：在图像感测装置内形成相邻的非重叠CCD电极的方法和装置，如电极是U形的。通过所公开的方法提供的装置采用在基板的表面上形成有在CCD内产生多个相的栅介电层的基板。将沉积的硅层放置在CCD的表面上，并且掩模用于覆盖除第一组电极之外的区域。蚀刻将掩模区域留在沉积的硅上，然后将一组侧壁与剩余的沉积的硅氧化。通过形成放置在CCD上的电极层的第一组电极。 CMP被用于去除剩余的沉积硅层以及电极层的一部分，使得侧壁保持垂直于保留在侧壁中的电极层的部分。然后通过放置另外的电极材料层和另一个CMP工艺留下两组相邻的U形门来重复该过程。

3. 发明授权

US06627107B2 Slurry for chemical mechanical polishing silicon dioxide 有权
公开(公告)号：US06627107B2
公开(公告)日：2003-09-30
申请号：US10192471
申请日：2002-07-10
申请人： Ramanathan Srinivasan , Suryadevara V. Babu , William G. America , Yie-Shein Her
发明人： Ramanathan Srinivasan , Suryadevara V. Babu , William G. America , Yie-Shein Her
IPC分类号： C09K1302
CPC分类号： C09G1/02
摘要： A new slurry for shallow trench isolation (STI) processing in the chemical mechanical planarization (CMP) in microelectronic industry comprising an aqueous medium having an abrasive; and a compound which has a carboxylic group and an electrophilic functional group. The combination of ceria and/or titania with amino acids to obtain polishing selectivity's greater than 5:1. CMP is used for removing the excess oxide and planarizing the substrate and the trench. The silicon nitride acts as a stop layer, preventing the polishing of underlying silicon substrate.

4. 发明授权

US06489642B1 Image sensor having improved spectral response uniformity 有权
标题翻译：图像传感器具有改进的光谱响应均匀性
公开(公告)号：US06489642B1
公开(公告)日：2002-12-03
申请号：US09672246
申请日：2000-09-28
申请人： William G. America , Christopher R. Hoople , Loretta R. Fendrock , Stephen L. Kosman
发明人： William G. America , Christopher R. Hoople , Loretta R. Fendrock , Stephen L. Kosman
IPC分类号： H01L27148
CPC分类号： H01L31/022466 , H01L27/14806 , H01L31/022475
摘要： An image sensor, includes a semiconductor substrate; a photosensor having, a first photosensing region including a first stack of one or more layers of transparent materials overlying the substrate, the first photosensing region having a spectral response having peaks and valleys, and a second photosensing region including a second stack of one or more layers of transparent materials overlying the substrate, the second photosensing region having a spectral response having peaks and valleys; and wherein at least one peak or valley of the spectral response of the first region is matched to at least one valley or peak respectively of the spectral response of the second region such that the average spectral response of the photosensor is smoother than the individual spectral response of either the first or second photosensing regions.
摘要翻译：一种图像传感器，包括半导体衬底; 光传感器，其具有第一光敏区域，该第一光敏区域包括覆盖在所述衬底上的一层或多层透明材料的第一叠层，所述第一光敏区域具有峰值和谷值的光谱响应，以及第二光敏区域，所述第二光敏区域包括一个或多个覆盖在衬底上的透明材料层，第二光敏区域具有峰和谷的光谱响应; 并且其中第一区域的光谱响应的至少一个峰值或谷值分别与第二区域的光谱响应的至少一个谷或峰匹配，使得光电传感器的平均光谱响应比各个光谱响应更平滑第一或第二光敏区域。

5. 发明授权

US06403993B1 Charge coupled image sensor with u-shaped gates 有权
标题翻译：电荷耦合图像传感器与u形门
公开(公告)号：US06403993B1
公开(公告)日：2002-06-11
申请号：US09443011
申请日：1999-11-18
申请人： David L. Losee , William G. America
发明人： David L. Losee , William G. America
IPC分类号： H01L27148
CPC分类号： H01L27/14812
摘要： A method and apparatus of forming adjacent, non-overlapping CCD electrodes within an image sensing device such the electrodes are U-shaped. The device provided by the disclosed method employs a substrate with a gate dielectric layer formed on a surface of the substrate with a plurality of phases created within the CCD. A deposited silicon layer is placed on the surface of the CCD and a mask is used to cover areas other than the first set of electrodes. Etching takes places leaving the mask areas to the deposited silicon and a set of side walls to the remaining deposited silicon are then oxidized. A first set of electrodes by forming an electrode layer placed over the CCD. CMP is employed to remove remaining deposited silicon layer as well as portions of the electrode layer such that the side walls remain vertical portions to electrode layer remaining in the side walls. The process is then repeated by placing another electrode material layer and another CMP process leaving two sets of adjacent U-shaped gates.
摘要翻译：在图像感测装置内形成相邻的非重叠CCD电极的方法和装置，如电极是U形的。通过所公开的方法提供的装置采用在基板的表面上形成有在CCD内产生多个相的栅介电层的基板。将沉积的硅层放置在CCD的表面上，并且掩模用于覆盖除第一组电极之外的区域。蚀刻将掩模区域留在沉积的硅上，然后将一组侧壁与剩余的沉积的硅氧化。通过形成放置在CCD上的电极层的第一组电极。 CMP被用于去除剩余的沉积硅层以及电极层的一部分，使得侧壁保持垂直于保留在侧壁中的电极层的部分。然后通过放置另外的电极材料层和另一个CMP工艺留下两组相邻的U形门来重复该过程。

6. 发明授权

US5270125A Boron nutride membrane in wafer structure 失效
标题翻译：硼硅胶膜晶圆结构
公开(公告)号：US5270125A
公开(公告)日：1993-12-14
申请号：US782705
申请日：1991-10-25
申请人： William G. America , Richard R. Poole
发明人： William G. America , Richard R. Poole
IPC分类号： C23C16/34 , G01N25/18 , G03F1/22 , B32B9/00 , G03F9/00
CPC分类号： B81B3/0021 , C23C16/342 , G01N25/18 , G03F1/22 , B81B2201/0214 , B81B2201/0278 , B81B2201/052 , B81B2201/054 , B81B2203/0127 , B81B2203/0315 , Y10T428/24612 , Y10T428/24777
摘要： A laminated structure includes a wafer member with a membrane attached thereto, the membrane being formed of substantially hydrogen-free boron nitride having a nominal composition B.sub.3 N. The structure may be a component in a mechanical device for effecting a mechanical function, or the membrane may form a masking layer on the wafer. The structure includes a body formed of at least two wafer members laminated together with a cavity formed therebetween, with the boron nitride membrane extending into the cavity so as to provide the structural component such as a support for a heating element or a membrane in a gas valve. In another aspect borom is selectively diffused from the boron nitride into a surface of a silicon wafer. The surface is then exposed to EDP etchant to which the diffusion layer is resistant, thereby forming a channel the wafer member with smooth walls for fluid flow.
摘要翻译：叠层结构包括具有膜的膜片构件，膜由具有标称组成B3N的基本上无氢的氮化硼形成。该结构可以是用于实现机械功能的机械装置中的部件，或者膜可以在晶片上形成掩模层。该结构包括由至少两个晶片构件形成的主体，所述至少两个晶片构件在其间形成有腔，其中氮化硼膜延伸到空腔中，以便提供结构部件，例如气体中的加热元件或膜的支撑体阀。在另一方面，硼化物选择性地从氮化硼扩散到硅晶片的<100>表面。然后将表面暴露于扩散层所抵抗的EDP蚀刻剂，从而形成具有平滑壁用于流体流动的晶片构件的通道。

7. 发明授权

US4587014A Liquid chromatography column assembly 失效
标题翻译：液相色谱柱组件
公开(公告)号：US4587014A
公开(公告)日：1986-05-06
申请号：US607878
申请日：1984-05-07
申请人： William G. America
发明人： William G. America
IPC分类号： B01D15/08 , G01N30/56 , G01N30/60
CPC分类号： G01N30/6004 , G01N30/56
摘要： A liquid chromatography column assembly includes a separation column having stationary phase retaining frits is positioned within a housing adapted to accept conventional column termination fittings. The assembly includes a sealed cylindrical cavity to ensure radial distribution of the incoming fluid across the cross-section of the column.
摘要翻译：液相色谱柱组件包括具有固定相保留玻璃料的分离柱，其定位在适于接受常规柱终止接头的壳体内。组件包括密封的圆柱形腔，以确保进入的流体在柱的横截面上的径向分布。

8. 发明授权

US08106485B2 Chemical oxide removal of plasma damaged SiCOH low k dielectrics 有权
标题翻译：化学氧化物去除等离子体损坏的SiCOH低k电介质
公开(公告)号：US08106485B2
公开(公告)日：2012-01-31
申请号：US12044245
申请日：2008-03-07
申请人： William G. America , Steven H. Johnston , Brian W. Messenger
发明人： William G. America , Steven H. Johnston , Brian W. Messenger
IPC分类号： H01L29/06 , H01L21/44
CPC分类号： H01L21/312 , H01L21/02063 , H01L21/02126 , H01L21/31633 , H01L21/76814
摘要： A structure and method for removing damages of a dual damascene structure after plasma etching. The method includes the use of sublimation processes to deposit reactive material onto the damaged regions and conditions to achieve a controlled removal of the damaged region. Furthermore a semiconductor structure includes a dual damascene structure that has been treated by the method.
摘要翻译：等离子蚀刻后去除双镶嵌结构损坏的结构和方法。该方法包括使用升华过程将反应性材料沉积在受损区域上并实现受损区域的受控去除的条件。此外，半导体结构包括已经通过该方法处理的双镶嵌结构。

9. 发明授权

US06875688B1 Method for reactive ion etch processing of a dual damascene structure 失效
标题翻译：双镶嵌结构的反应离子蚀刻处理方法
公开(公告)号：US06875688B1
公开(公告)日：2005-04-05
申请号：US10709630
申请日：2004-05-18
申请人： William G. America , Kaushik A. Kumar
发明人： William G. America , Kaushik A. Kumar
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76835 , H01L21/76811 , H01L21/76813 , H01L21/76829
摘要： A method for implementing dual damascene processing includes forming a first hardmask layer over an interlevel dielectric layer, and forming a second hardmask layer over the first hardmask layer. A trench pattern is opened within a third hardmask layer formed over the second hardmask. A first etch process is implemented so as to define a via pattern completely through the second hardmask layer and partially through the first hardmask layer, and a second etch process is implemented to transfer the trench pattern and the via pattern into the interlevel dielectric layer.
摘要翻译：一种用于实现双镶嵌处理的方法包括在层间介质层上形成第一硬掩模层，以及在第一硬掩模层上形成第二硬掩模层。沟槽图案在形成在第二硬掩模上的第三硬掩模层内打开。实施第一蚀刻工艺以便通过第二硬掩模层完全定义通孔图案并且部分地穿过第一硬掩模层，并且实施第二蚀刻工艺以将沟槽图案和通孔图案转移到层间电介质层中。

10. 发明授权

US07368393B2 Chemical oxide removal of plasma damaged SiCOH low k dielectrics 有权
标题翻译：化学氧化物去除等离子体损坏的SiCOH低k电介质
公开(公告)号：US07368393B2
公开(公告)日：2008-05-06
申请号：US11308672
申请日：2006-04-20
申请人： William G. America , Steven H. Johnston , Brian W. Messenger
发明人： William G. America , Steven H. Johnston , Brian W. Messenger
IPC分类号： H01L21/3065
CPC分类号： H01L21/312 , H01L21/02063 , H01L21/02126 , H01L21/31633 , H01L21/76814
摘要： A method for removing damages of a dual damascene structure after plasma etching is disclosed. The method comprises the use of sublimation processes to deposit reactive material onto the damaged regions and conditions to achieve a controlled removal of the damaged region. Furthermore a semiconductor structure comprising a dual damascene structure that has been treated by the method is disclosed.
摘要翻译：公开了一种在等离子体蚀刻之后去除双镶嵌结构的损坏的方法。该方法包括使用升华过程将反应性材料沉积在受损区域上并实现对受损区域的控制去除的条件。此外，公开了一种包括已经通过该方法处理的双镶嵌结构的半导体结构。

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