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1. 发明申请

US20100036997A1 MULTIPLE DATA CHANNEL MEMORY MODULE ARCHITECTURE 有权
标题翻译：多个数据通道存储器模块架构
公开(公告)号：US20100036997A1
公开(公告)日：2010-02-11
申请号：US12186372
申请日：2008-08-05
申请人： Tony M. Brewer , J. Michael Andrewartha , William D. O'Leary , Michael K. Dugan
发明人： Tony M. Brewer , J. Michael Andrewartha , William D. O'Leary , Michael K. Dugan
IPC分类号： G06F12/06
CPC分类号： G06F12/0811 , G06F12/04 , G06F12/0607 , G06F2212/283 , G11C7/1072
摘要： The present invention is directed generally to systems and methods which provide a memory module having multiple data channels that are independently accessible (i.e., a multi-data channel memory module). According to one embodiment, the multi-data channel memory module enables a plurality of independent sub-cache-block accesses to be serviced simultaneously. In addition, the memory architecture also supports cache-block accesses. For instance, multiple ones of the data channels may be employed for servicing a cache-block access. In one embodiment a DIMM architecture that comprises multiple data channels is provided. Each data channel supports a sub-cache-block access, and multiple ones of the data channels may be used for supporting a cache-block access. The plurality of data channels to a given DIMM may be used simultaneously to support different, independent memory access operations.
摘要翻译：本发明一般涉及提供具有独立可访问的多个数据信道（即，多数据信道存储器模块）的存储器模块的系统和方法。根据一个实施例，多数据通道存储器模块使多个独立的子高速缓存块访问同时被服务。此外，内存架构还支持高速缓存块访问。例如，可以使用多个数据信道来服务高速缓存块访问。在一个实施例中，提供了包括多个数据通道的DIMM架构。每个数据信道支持子缓存块访问，并且可以使用多个数据信道来支持高速缓存块访问。给定DIMM的多个数据信道可以同时使用以支持不同的独立存储器访问操作。

2. 发明授权

US06711357B1 Timing and synchronization for an IP router using an optical switch 失效
标题翻译：使用光开关的IP路由器的时序和同步
公开(公告)号：US06711357B1
公开(公告)日：2004-03-23
申请号：US09702958
申请日：2000-10-31
申请人： Tony Brewer , Harry C. Blackmon , Harold W. Dozier , William D. O'Leary , Dean E. Walker
发明人： Tony Brewer , Harry C. Blackmon , Harold W. Dozier , William D. O'Leary , Dean E. Walker
IPC分类号： H04J1400
CPC分类号： H04Q11/0005 , H04L49/101 , H04L49/254 , H04L49/30 , H04L49/552 , H04Q11/0066
摘要： Information and control are synchronized as they flow through a large distributed IP router system with independent clocks. The IP router includes multiple equipment racks and shelves, each containing multiple modules. The IP router is based on a passive switching device, which in some embodiments is an optical switch. Control and data come to the switching device from different sources, which have different clocks. Timing and synchronization control are provided, such that information and control both arrive at the switching device at the proper time. A single point in the system originates timing, which is then distributed through various ASICs of the system to deliver configuration control to the switch at the appropriate time. The launch of information to the switch is also controlled with a dynamic feedback loop from an optical switch controller. Control aspects of the optical switch are aligned by this same mechanism to deliver control and data to the optical switch simultaneously.
摘要翻译：当信息和控制流经独立时钟的大型分布式IP路由器系统时，信息和控制是同步的。 IP路由器包括多个设备机架和货架，每个包含多个模块。 IP路由器基于无源交换设备，其在一些实施例中是光学交换机。来自不同来源的控制和数据来自具有不同时钟的开关装置。提供定时和同步控制，使得信息和控制在适当的时间到达切换设备。系统中的一个点产生定时，然后通过系统的各种ASIC进行分配，以便在适当的时间向交换机提供配置控制。通过光开关控制器的动态反馈回路也可以控制开关信号的启动。光开关的控制方面通过相同的机构对准，以将控制和数据同时传送到光开关。

3. 发明授权

US09015399B2 Multiple data channel memory module architecture 有权
标题翻译：多数据通道内存模块架构
公开(公告)号：US09015399B2
公开(公告)日：2015-04-21
申请号：US12186372
申请日：2008-08-05
申请人： Tony M. Brewer , J. Michael Andrewartha , William D. O'Leary , Michael K. Dugan
发明人： Tony M. Brewer , J. Michael Andrewartha , William D. O'Leary , Michael K. Dugan
IPC分类号： G06F12/06 , G06F12/04
CPC分类号： G06F12/0811 , G06F12/04 , G06F12/0607 , G06F2212/283 , G11C7/1072
摘要： The present invention is directed generally to systems and methods which provide a memory module having multiple data channels that are independently accessible (i.e., a multi-data channel memory module). According to one embodiment, the multi-data channel memory module enables a plurality of independent sub-cache-block accesses to be serviced simultaneously. In addition, the memory architecture also supports cache-block accesses. For instance, multiple ones of the data channels may be employed for servicing a cache-block access. In one embodiment a DIMM architecture that comprises multiple data channels is provided. Each data channel supports a sub-cache-block access, and multiple ones of the data channels may be used for supporting a cache-block access. The plurality of data channels to a given DIMM may be used simultaneously to support different, independent memory access operations.
摘要翻译：本发明一般涉及提供具有独立可访问的多个数据信道（即，多数据信道存储器模块）的存储器模块的系统和方法。根据一个实施例，多数据通道存储器模块使多个独立的子高速缓存块访问同时被服务。此外，内存架构还支持高速缓存块访问。例如，可以使用多个数据信道来服务高速缓存块访问。在一个实施例中，提供了包括多个数据通道的DIMM架构。每个数据信道支持子缓存块访问，并且可以使用多个数据信道来支持高速缓存块访问。给定DIMM的多个数据信道可以同时使用以支持不同的独立存储器访问操作。

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