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1. 发明申请

US20090003451A1 SHARED PIPELINE ARCHITECTURE FOR MOTION VECTOR PREDICTION AND RESIDUAL DECODING 审中-公开
标题翻译：用于运动矢量预测和残留解码的共享管道结构
公开(公告)号：US20090003451A1
公开(公告)日：2009-01-01
申请号：US12195344
申请日：2008-08-20
申请人： Teng Chiang Lin , Weimin Zeng
发明人： Teng Chiang Lin , Weimin Zeng
IPC分类号： H04N7/26
CPC分类号： H04N19/93 , H04N19/42 , H04N19/52
摘要： A shared pipeline architecture is provided for H.264 motion vector prediction and residual decoding, and intra prediction for CABAC and CALVC entropy in Main Profile and High Profile for standard and high definition applications. All motion vector predictions and residual decoding of I-type, P-type, and B-type pictures are completed through the shared pipeline. The architecture enables better performance and uses less memory than conventional architectures. The architecture can be completely implemented in hardware as a system-on-chip or chip set using, for example, field programmable gate array (FPGA) technology or application specific integrated circuitry (ASIC) or other custom-built logic.
摘要翻译：提供了用于H.264运动矢量预测和残差解码的共享流水线架构，以及用于标准和高清应用的主轮廓和高轮廓中的CABAC和CALVC熵的帧内预测。通过共享管道完成I型，P型和B型图像的所有运动矢量预测和残差解码。该架构能够实现更好的性能，并且比传统架构使用更少的内存。该架构可以使用例如现场可编程门阵列（FPGA）技术或专用集成电路（ASIC）或其他定制逻辑来作为片上系统或芯片集而在硬件中完全实现。

2. 发明授权

US07430238B2 Shared pipeline architecture for motion vector prediction and residual decoding 失效
标题翻译：用于运动矢量预测和残差解码的共享流水线架构
公开(公告)号：US07430238B2
公开(公告)日：2008-09-30
申请号：US11138849
申请日：2005-05-25
申请人： Teng Chiang Lin , Weimin Zeng
发明人： Teng Chiang Lin , Weimin Zeng
IPC分类号： H04N7/12
CPC分类号： H04N19/93 , H04N19/42 , H04N19/52
摘要： A shared pipeline architecture is provided for H.264 motion vector prediction and residual decoding, and intra prediction for CABAC and CALVC entropy in Main Profile and High Profile for standard and high definition applications. All motion vector predictions and residual decoding of I-type, P-type, and B-type pictures are completed through the shared pipeline. The architecture enables better performance and uses less memory than conventional architectures. The architecture can be completely implemented in hardware as a system-on-chip or chip set using, for example, field programmable gate array (FPGA) technology or application specific integrated circuitry (ASIC) or other custom-built logic.
摘要翻译：提供了用于H.264运动矢量预测和残差解码的共享流水线架构，以及用于标准和高清应用的主轮廓和高轮廓中的CABAC和CALVC熵的帧内预测。通过共享管道完成I型，P型和B型图像的所有运动矢量预测和残差解码。该架构能够实现更好的性能，并且比传统架构使用更少的内存。该架构可以使用例如现场可编程门阵列（FPGA）技术或专用集成电路（ASIC）或其他定制逻辑来作为片上系统或芯片集而在硬件中完全实现。

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