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1. 发明授权

US08030706B2 Power semiconductor device 失效
标题翻译：功率半导体器件
公开(公告)号：US08030706B2
公开(公告)日：2011-10-04
申请号：US12540192
申请日：2009-08-12
申请人： Miho Watanabe , Masaru Izumisawa , Yasuto Sumi , Hiroshi Ohta , Wataru Sekine , Wataru Saito , Syotaro Ono , Nana Hatano
发明人： Miho Watanabe , Masaru Izumisawa , Yasuto Sumi , Hiroshi Ohta , Wataru Sekine , Wataru Saito , Syotaro Ono , Nana Hatano
IPC分类号： H01L29/66
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/1095 , H01L29/7802
摘要： A semiconductor device according to an embodiment of the present invention includes a device part and a terminal part. The device includes a first semiconductor layer, and second and third semiconductor layers formed on the first semiconductor layer, and alternately arranged along a direction parallel to a surface of the first semiconductor layer, wherein the device part is provided with a first region and a second region, each of which includes at least one of the second semiconductor layers and at least one of the third semiconductor layers, and with regard to a difference value ΔN (=NA−NB) obtained by subtracting an impurity amount NB per unit length of each of the third semiconductor layers from an impurity amount NA per unit length of each of the second semiconductor layers, a difference value ΔNC1 which is the difference value ΔN in the first region of the device part, a difference value ΔNC2 which is the difference value ΔN in the second region of the device part, and a difference value ΔNT which is the difference value ΔN in the terminal part satisfy a relationship of ΔNC1>ΔNT>ΔNC2.
摘要翻译：根据本发明实施例的半导体器件包括器件部分和端子部分。该器件包括第一半导体层，以及形成在第一半导体层上的第二和第三半导体层，并且沿着与第一半导体层的表面平行的方向交替布置，其中器件部分设置有第一区域和第二半导体层区域，其中每一个包括第二半导体层和至少一个第三半导体层中的至少一个，并且关于通过从每单位长度减去杂质量NB获得的差值Dgr; N（= NA-NB）从每个第二半导体层的每单位长度的杂质量NA中的每个第三半导体层的差分值＆Dgr; NC1，其是器件部分的第一区域中的差值＆Dgr; N，差值＆Dgr ;作为装置部分的第二区域中的差值Dgr; N的NC2，作为终端部分中的差值Dgr; N的差值＆Dgr; NT满足关系的＆Dgr; NC1>＆Dgr; NT>＆Dgr; NC2。

2. 发明申请

US20110018055A1 POWER SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 失效
标题翻译：功率半导体器件及其制造方法
公开(公告)号：US20110018055A1
公开(公告)日：2011-01-27
申请号：US12840201
申请日：2010-07-20
申请人： Hiroshi OHTA , Yasuto SUMI , Kiyoshi KIMURA , Wataru SEKINE , Wataru SAITO , Syotaro ONO , Munehisa YABUZAKI , Nana HATANO , Miho WATANABE
发明人： Hiroshi OHTA , Yasuto SUMI , Kiyoshi KIMURA , Wataru SEKINE , Wataru SAITO , Syotaro ONO , Munehisa YABUZAKI , Nana HATANO , Miho WATANABE
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66712 , H01L29/0619 , H01L29/0634 , H01L29/0638 , H01L29/0696 , H01L29/1095 , H01L29/402 , H01L29/7811
摘要： According to one embodiment, a power semiconductor device includes a first semiconductor layer, and first, second and third semiconductor regions. The first semiconductor layer has a first conductivity type. The first semiconductor regions have a second conductivity type, and are formed with periodicity in a lateral direction in a second semiconductor layer of the first conductivity type. The second semiconductor layer is provided on a major surface of the first semiconductor layer in a device portion with a main current path formed in a vertical direction generally perpendicular to the major surface and in a terminal portion provided around the device portion. The second semiconductor region has the first conductivity type and is a portion of the second semiconductor layer sandwiched between adjacent ones of the first semiconductor regions. The third semiconductor regions have the second conductivity type and are provided below the first semiconductor regions in the terminal portion.
摘要翻译：根据一个实施例，功率半导体器件包括第一半导体层以及第一，第二和第三半导体区域。第一半导体层具有第一导电类型。第一半导体区域具有第二导电类型，并且在第一导电类型的第二半导体层中在横向方向上形成周期性。第二半导体层设置在器件部分的第一半导体层的主表面上，其主电流通道形成在大体上垂直于主表面的垂直方向上，以及设置在器件部分周围的端子部分中。第二半导体区域具有第一导电类型，并且是夹在相邻的第一半导体区域中的第二半导体层的一部分。第三半导体区域具有第二导电类型并且设置在端子部分中的第一半导体区域的下方。

3. 发明授权

US07622771B2 Semiconductor apparatus 失效
标题翻译：半导体装置
公开(公告)号：US07622771B2
公开(公告)日：2009-11-24
申请号：US12123072
申请日：2008-05-19
申请人： Syotaro Ono , Wataru Saito , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta , Wataru Sekine
发明人： Syotaro Ono , Wataru Saito , Masakatsu Takashita , Yasuto Sumi , Masaru Izumisawa , Hiroshi Ohta , Wataru Sekine
IPC分类号： H01L31/119 , H01L21/336
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0638 , H01L29/0878 , H01L29/7395 , H01L29/861 , H01L29/868 , H01L29/872
摘要： A semiconductor apparatus includes a first semiconductor layer, a second semiconductor layer provided on a major surface of the first semiconductor layer, a third semiconductor layer provided on the major surface and being adjacent to the second semiconductor layer, a termination semiconductor layer provided on the major surface of the first semiconductor layer in a termination region outside the device region, a channel stop layer, and a channel stop electrode. The channel stop layer is provided in contact with the termination semiconductor layer on the major surface of the first semiconductor layer in an outermost peripheral portion outside the termination semiconductor layer and has a higher impurity concentration than the termination semiconductor layer. The channel stop electrode is provided on at least part of a surface of the channel stop layer and projects toward the termination semiconductor layer beyond at least a superficial portion of the channel stop layer.
摘要翻译：半导体装置包括第一半导体层，设置在第一半导体层的主表面上的第二半导体层，设置在主表面上并与第二半导体层相邻的第三半导体层，设置在主体上的端接半导体层在器件区域外的终端区域中的第一半导体层的表面，沟道阻挡层和沟道停止电极。沟道阻挡层设置成与终端半导体层外部的最外周部分中的第一半导体层的主表面上的端接半导体层接触，并且具有比端接半导体层更高的杂质浓度。通道阻挡电极设置在通道阻挡层的表面的至少一部分上，并且朝向端子半导体层突出超过通道阻挡层的至少表面部分。

4. 发明申请

US20090236697A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090236697A1
公开(公告)日：2009-09-24
申请号：US12403881
申请日：2009-03-13
申请人： Syotaro ONO , Wataru SAITO , Nana HATANO , Masaru IZUMISAWA , Yasuto SUMI , Hiroshi OHTA , Wataru SEKINE , Miho WATANABE
发明人： Syotaro ONO , Wataru SAITO , Nana HATANO , Masaru IZUMISAWA , Yasuto SUMI , Hiroshi OHTA , Wataru SEKINE , Miho WATANABE
IPC分类号： H01L29/06 , H01L21/20
CPC分类号： H01L29/66712 , H01L21/266 , H01L29/0615 , H01L29/0634 , H01L29/0638 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/7395 , H01L29/7811
摘要： A semiconductor device includes a super junction region that has a first-conductivity-type first semiconductor pillar region and a second-conductivity-type second semiconductor pillar region alternately provided on the semiconductor substrate. The first semiconductor pillar region and the second semiconductor pillar region in a termination region have a lamination form resulting from alternate lamination of the first semiconductor pillar region and the second semiconductor pillar region on the top surface of the semiconductor substrate. The first semiconductor pillar region and/or the second semiconductor pillar region at a corner part of the termination region exhibit an impurity concentration distribution such that a plurality of impurity concentration peaks appear periodically. The first semiconductor pillar region and/or the second semiconductor pillar region at a corner part of the termination region have an impurity amount such that it becomes smaller as being closer to the circumference of the corner part.
摘要翻译：半导体器件包括具有交替设置在半导体衬底上的第一导电型第一半导体柱区域和第二导电型第二半导体柱区域的超结区域。终端区域中的第一半导体柱区域和第二半导体柱区域具有由半导体衬底的顶表面上的第一半导体柱区域和第二半导体柱区域的交替层叠形成的叠层形式。终端区域的角部处的第一半导体柱区域和/或第二半导体柱区域显示杂质浓度分布，使得多个杂质浓度峰值周期性出现。终端区域的角部处的第一半导体柱区域和/或第二半导体柱区域具有使得随着角部更靠近圆周而变小的杂质量。

5. 发明申请

US20080246079A1 POWER SEMICONDUCTOR DEVICE 有权
标题翻译：功率半导体器件
公开(公告)号：US20080246079A1
公开(公告)日：2008-10-09
申请号：US12050415
申请日：2008-03-18
申请人： Wataru Saito , Syotaro Ono , Masakatsu Takashita , Yauto Sumi , Masaru Izumisawa , Wataru Sekine , Hiroshi Ohta , Shoichiro Kurushima
发明人： Wataru Saito , Syotaro Ono , Masakatsu Takashita , Yauto Sumi , Masaru Izumisawa , Wataru Sekine , Hiroshi Ohta , Shoichiro Kurushima
IPC分类号： H01L29/00
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0878 , H01L29/1095
摘要： A power semiconductor device includes: a first semiconductor layer; a second semiconductor layer and a third semiconductor layer provided in an upper portion of the first semiconductor layer and alternately arranged parallel to an upper surface of the first semiconductor layer; a plurality of fourth semiconductor layers provided on the third semiconductor layer; a fifth semiconductor layer selectively formed in an upper surface of each of the fourth semiconductor layers; a control electrode; a gate insulating film; a first main electrode provided on a lower surface of the first semiconductor layer; and a second main electrode provided on the fourth and the fifth semiconductor layers. Sum of the amount of impurities in the second semiconductor layer and the amount of impurities in the third semiconductor layer at an end on the second main electrode side of the second semiconductor layer and the third semiconductor layer is smaller than the sum at a center of the second semiconductor layer and the third semiconductor layer in the direction from the first main electrode to the second main electrode.
摘要翻译：功率半导体器件包括：第一半导体层; 第二半导体层和第三半导体层，设置在所述第一半导体层的上部并且交替地平行于所述第一半导体层的上表面布置; 设置在所述第三半导体层上的多个第四半导体层; 选择性地形成在每个第四半导体层的上表面中的第五半导体层; 控制电极; 栅极绝缘膜; 设置在所述第一半导体层的下表面上的第一主电极; 以及设置在第四和第五半导体层上的第二主电极。第二半导体层中的杂质量和第二半导体层的第二主电极侧端部的第三半导体层中的杂质量的和小于第二半导体层的第二主电极侧的和第二半导体层和第三半导体层在从第一主电极到第二主电极的方向上。

6. 发明申请

US20100038712A1 POWER SEMICONDUCTOR DEVICE 失效
标题翻译：功率半导体器件
公开(公告)号：US20100038712A1
公开(公告)日：2010-02-18
申请号：US12540192
申请日：2009-08-12
申请人： Miho WATANABE , Masaru IZUMISAWA , Yasuto SUMI , Hiroshi OHTA , Wataru SEKINE , Wataru SAITO , Syotaro ONO , Nana HATANO
发明人： Miho WATANABE , Masaru IZUMISAWA , Yasuto SUMI , Hiroshi OHTA , Wataru SEKINE , Wataru SAITO , Syotaro ONO , Nana HATANO
IPC分类号： H01L29/78
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/1095 , H01L29/7802
摘要： A semiconductor device according to an embodiment of the present invention includes a device part and a terminal part. The device includes a first semiconductor layer, and second and third semiconductor layers formed on the first semiconductor layer, and alternately arranged along a direction parallel to a surface of the first semiconductor layer, wherein the device part is provided with a first region and a second region, each of which includes at least one of the second semiconductor layers and at least one of the third semiconductor layers, and with regard to a difference value ΔN (=NA−NB) obtained by subtracting an impurity amount NB per unit length of each of the third semiconductor layers from an impurity amount NA per unit length of each of the second semiconductor layers, a difference value ΔNC1 which is the difference value ΔN in the first region of the device part, a difference value ΔNC2 which is the difference value ΔN in the second region of the device part, and a difference value ΔNT which is the difference value ΔN in the terminal part satisfy a relationship of ΔNC1>ΔNT>ΔNC2.
摘要翻译：根据本发明实施例的半导体器件包括器件部分和端子部分。该器件包括第一半导体层，以及形成在第一半导体层上的第二和第三半导体层，并且沿着与第一半导体层的表面平行的方向交替布置，其中器件部分设置有第一区域和第二半导体层区域，其中每一个包括第二半导体层和至少一个第三半导体层中的至少一个，并且关于通过从每单位长度减去杂质量NB获得的差值Dgr; N（= NA-NB）从每个第二半导体层的每单位长度的杂质量NA中的每个第三半导体层的差分值＆Dgr; NC1，其是器件部分的第一区域中的差值＆Dgr; N，差值＆Dgr ;作为装置部分的第二区域中的差值Dgr; N的NC2，作为终端部分中的差值Dgr; N的差值＆Dgr; NT满足关系的＆Dgr; NC1>＆Dgr; NT>＆Dgr; NC2。

7. 发明授权

US08283720B2 Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：US08283720B2
公开(公告)日：2012-10-09
申请号：US12050415
申请日：2008-03-18
申请人： Wataru Saito , Syotaro Ono , Masakatsu Takashita , Yauto Sumi , Masaru Izumisawa , Wataru Sekine , Hiroshi Ohta , Shoichiro Kurushima
发明人： Wataru Saito , Syotaro Ono , Masakatsu Takashita , Yauto Sumi , Masaru Izumisawa , Wataru Sekine , Hiroshi Ohta , Shoichiro Kurushima
IPC分类号： H01L29/00 , H01L29/66
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0878 , H01L29/1095
摘要： A power semiconductor device includes: a first semiconductor layer; a second semiconductor layer and a third semiconductor layer provided in an upper portion of the first semiconductor layer and alternately arranged parallel to an upper surface of the first semiconductor layer; a plurality of fourth semiconductor layers provided on the third semiconductor layer; a fifth semiconductor layer selectively formed in an upper surface of each of the fourth semiconductor layers; a control electrode; a gate insulating film; a first main electrode provided on a lower surface of the first semiconductor layer; and a second main electrode provided on the fourth and the fifth semiconductor layers. Sum of the amount of impurities in the second semiconductor layer and the amount of impurities in the third semiconductor layer at an end on the second main electrode side of the second semiconductor layer and the third semiconductor layer is smaller than the sum at a center of the second semiconductor layer and the third semiconductor layer in the direction from the first main electrode to the second main electrode.
摘要翻译：功率半导体器件包括：第一半导体层; 第二半导体层和第三半导体层，设置在所述第一半导体层的上部并且交替地平行于所述第一半导体层的上表面布置; 设置在所述第三半导体层上的多个第四半导体层; 选择性地形成在每个第四半导体层的上表面中的第五半导体层; 控制电极; 栅极绝缘膜; 设置在所述第一半导体层的下表面上的第一主电极; 以及设置在第四和第五半导体层上的第二主电极。第二半导体层中的杂质量和第二半导体层的第二主电极侧端部的第三半导体层中的杂质量的和小于第二半导体层的第二主电极侧的和第二半导体层和第三半导体层在从第一主电极到第二主电极的方向上。

8. 发明申请

US20120056101A1 ION DOPING APPARATUS AND ION DOPING METHOD 审中-公开
标题翻译：离子发射装置和离子掺杂方法
公开(公告)号：US20120056101A1
公开(公告)日：2012-03-08
申请号：US13219189
申请日：2011-08-26
申请人： Erumu KIKUCHI , Wataru SEKINE
发明人： Erumu KIKUCHI , Wataru SEKINE
IPC分类号： H01J27/16
CPC分类号： H01J27/20
摘要： When hydrogen is introduced into a plasma chamber which includes the dielectric plate as part of an exterior wall, and surface waves are generated on the dielectric plate using microwaves, a region where negative hydrogen ions are easily generated is formed in the plasma chamber. Since only hydrogen negative ions each with a molecular weight of 1 are generated, only ions with the same mass can be added to an object by application of an electric field, without mass separation.
摘要翻译：当氢气被引入包括作为外壁的一部分的电介质板的等离子体室中，并且在使用微波的电介质板上产生表面波时，在等离子体室中形成容易产生负的氢离子的区域。由于仅产生分子量为1的氢负离子，因此只有具有相同质量的离子才能通过施加电场而不进行质量分离而添加到物体中。

9. 发明授权

US07989910B2 Semiconductor device including a resurf region with forward tapered teeth 有权
标题翻译：半导体装置包括具有前锥形齿的复原区域
公开(公告)号：US07989910B2
公开(公告)日：2011-08-02
申请号：US12252872
申请日：2008-10-16
申请人： Wataru Saito , Syotaro Ono , Masaru Izumisawa , Yasuto Sumi , Hiroshi Ohta , Wataru Sekine , Nana Hatano
发明人： Wataru Saito , Syotaro Ono , Masaru Izumisawa , Yasuto Sumi , Hiroshi Ohta , Wataru Sekine , Nana Hatano
IPC分类号： H01L29/66
CPC分类号： H01L29/0634 , H01L29/0615 , H01L29/0638 , H01L29/0696 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/7811
摘要： A semiconductor device includes an n+ type semiconductor substrate 1 and a super junction region that has, on the top of the substrate 1, an n and p type pillar regions 2 and 3 provided alternately. The device also includes, in the top surface of the super junction region, a p type base region 4 and an n type source layer 5. The device also includes a gate electrode 7 on the region 4 and layer 5 via a gate-insulating film 6, a drain electrode 9 on the bottom of the substrate 1, and a source electrode 8 on the top of the substrate 1. In the top surface of the super junction region in the terminal region, a RESURF region 10 is formed. The RESURF region has a comb-like planar shape with repeatedly-formed teeth having tips facing the end portion of the terminal region.
摘要翻译：半导体器件包括n +型半导体衬底1和超结区，其在衬底1的顶部上交替设置n和p型柱状区域2,3。该器件还在超结区域的顶表面中包括ap型基极区域4和n型源极层5.该器件还包括位于区域4上的栅电极7和通过栅极绝缘膜6的层5 ，基板1底部的漏电极9以及基板1顶部的源极8.在端子区域的超结区域的上表面形成有RESURF区域10。 RESURF区域具有梳状平面形状，具有重复形成的齿，其尖端面向终端区域的端部。

10. 发明授权

US07919824B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07919824B2
公开(公告)日：2011-04-05
申请号：US12403881
申请日：2009-03-13
申请人： Syotaro Ono , Wataru Saito , Nana Hatano , Masaru Izumisawa , Yasuto Sumi , Hiroshi Ohta , Wataru Sekine , Miho Watanabe
发明人： Syotaro Ono , Wataru Saito , Nana Hatano , Masaru Izumisawa , Yasuto Sumi , Hiroshi Ohta , Wataru Sekine , Miho Watanabe
IPC分类号： H01L27/088
CPC分类号： H01L29/66712 , H01L21/266 , H01L29/0615 , H01L29/0634 , H01L29/0638 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/7395 , H01L29/7811
摘要： A semiconductor device includes a super junction region that has a first-conductivity-type first semiconductor pillar region and a second-conductivity-type second semiconductor pillar region alternately provided on the semiconductor substrate. The first semiconductor pillar region and the second semiconductor pillar region in a termination region have a lamination form resulting from alternate lamination of the first semiconductor pillar region and the second semiconductor pillar region on the top surface of the semiconductor substrate. The first semiconductor pillar region and/or the second semiconductor pillar region at a corner part of the termination region exhibit an impurity concentration distribution such that a plurality of impurity concentration peaks appear periodically. The first semiconductor pillar region and/or the second semiconductor pillar region at a corner part of the termination region have an impurity amount such that it becomes smaller as being closer to the circumference of the corner part.
摘要翻译：半导体器件包括具有交替设置在半导体衬底上的第一导电型第一半导体柱区域和第二导电型第二半导体柱区域的超结区域。终端区域中的第一半导体柱区域和第二半导体柱区域具有由半导体衬底的顶表面上的第一半导体柱区域和第二半导体柱区域的交替层叠形成的叠层形式。终端区域的角部处的第一半导体柱区域和/或第二半导体柱区域显示杂质浓度分布，使得多个杂质浓度峰值周期性出现。终端区域的角部处的第一半导体柱区域和/或第二半导体柱区域具有使得随着角部更靠近圆周而变小的杂质量。

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