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    • 1. 发明申请
    • SEMICONDUCTOR DEVICE
    • 半导体器件
    • US20070272979A1
    • 2007-11-29
    • US11748869
    • 2007-05-15
    • Wataru SAITOSyotaro OnoMasakatsu TakashitaYasuto SumiMasaru IzumisawaHiroshi OhtaWataru Sekine
    • Wataru SAITOSyotaro OnoMasakatsu TakashitaYasuto SumiMasaru IzumisawaHiroshi OhtaWataru Sekine
    • H01L29/76
    • H01L29/872H01L29/0619H01L29/0623H01L29/0634H01L29/0696H01L29/0878H01L29/402H01L29/404H01L29/41741H01L29/7395H01L29/7397H01L29/7722H01L29/7806H01L29/7811H01L29/8611
    • A semiconductor device includes: a semiconductor layer of a first conductivity type; a first semiconductor pillar region of the first conductivity type provided on a major surface of the semiconductor layer; a second semiconductor pillar region of a second conductivity type provided adjacent to the first semiconductor pillar region on the major surface of the semiconductor layer, the second semiconductor pillar region forming a periodic arrangement structure substantially parallel to the major surface of the semiconductor layer together with the first semiconductor pillar region; a first main electrode; a first semiconductor region of the second conductivity type; a second semiconductor region of the first conductivity type; a second main electrode; a control electrode; and a high-resistance semiconductor layer provided on the semiconductor layer in an edge termination section surrounding the first semiconductor pillar region and the second semiconductor pillar region. The high-resistance semiconductor layer has a lower dopant concentration than the first semiconductor pillar region. A boundary region is provided between a device central region and the edge termination section. The first semiconductor pillar region and the second semiconductor pillar region adjacent to the high-resistance semiconductor layer in the boundary region have a depth decreasing stepwise toward the edge termination section.
    • 半导体器件包括:第一导电类型的半导体层; 设置在半导体层的主表面上的第一导电类型的第一半导体柱区域; 第二导电类型的第二半导体柱区域,与半导体层的主表面上的第一半导体柱区域相邻设置,第二半导体柱区域形成基本上平行于半导体层的主表面的周期性排列结构以及 第一半导体柱区域; 第一主电极; 第二导电类型的第一半导体区域; 第一导电类型的第二半导体区域; 第二主电极; 控制电极; 以及设置在包围第一半导体柱区域和第二半导体柱区域的边缘终端部分的半导体层上的高电阻半导体层。 高电阻半导体层的掺杂浓度低于第一半导体柱区域。 边界区域设置在设备中心区域和边缘终端部分之间。 边界区域中与高电阻半导体层相邻的第一半导体柱区域和第二半导体柱区域具有沿着边缘终止部分逐步减小的深度。
    • 2. 发明授权
    • Semiconductor device having superjunction structure formed of p-type and n-type pillar regions
    • 具有由p型和n型柱状区域形成的超结构结构的半导体装置
    • US07737469B2
    • 2010-06-15
    • US11748869
    • 2007-05-15
    • Wataru SaitoSyotaro OnoMasakatsu TakashitaYasuto SumiMasaru IzumisawaHiroshi OhtaWataru Sekine
    • Wataru SaitoSyotaro OnoMasakatsu TakashitaYasuto SumiMasaru IzumisawaHiroshi OhtaWataru Sekine
    • H01L29/74
    • H01L29/872H01L29/0619H01L29/0623H01L29/0634H01L29/0696H01L29/0878H01L29/402H01L29/404H01L29/41741H01L29/7395H01L29/7397H01L29/7722H01L29/7806H01L29/7811H01L29/8611
    • A semiconductor device includes: a semiconductor layer of a first conductivity type; a first semiconductor pillar region of the first conductivity type provided on a major surface of the semiconductor layer; a second semiconductor pillar region of a second conductivity type provided adjacent to the first semiconductor pillar region on the major surface of the semiconductor layer, the second semiconductor pillar region forming a periodic arrangement structure substantially parallel to the major surface of the semiconductor layer together with the first semiconductor pillar region; a first main electrode; a first semiconductor region of the second conductivity type; a second semiconductor region of the first conductivity type; a second main electrode; a control electrode; and a high-resistance semiconductor layer provided on the semiconductor layer in an edge termination section surrounding the first semiconductor pillar region and the second semiconductor pillar region. The high-resistance semiconductor layer has a lower dopant concentration than the first semiconductor pillar region. A boundary region is provided between a device central region and the edge termination section. The first semiconductor pillar region and the second semiconductor pillar region adjacent to the high-resistance semiconductor layer in the boundary region have a depth decreasing stepwise toward the edge termination section.
    • 半导体器件包括:第一导电类型的半导体层; 设置在半导体层的主表面上的第一导电类型的第一半导体柱区域; 第二导电类型的第二半导体柱区域,与半导体层的主表面上的第一半导体柱区域相邻设置,第二半导体柱区域形成基本上平行于半导体层的主表面的周期性排列结构以及 第一半导体柱区域; 第一主电极; 第二导电类型的第一半导体区域; 第一导电类型的第二半导体区域; 第二主电极; 控制电极; 以及设置在包围第一半导体柱区域和第二半导体柱区域的边缘终端部分的半导体层上的高电阻半导体层。 高电阻半导体层的掺杂浓度低于第一半导体柱区域。 边界区域设置在设备中心区域和边缘终端部分之间。 边界区域中与高电阻半导体层相邻的第一半导体柱区域和第二半导体柱区域具有沿着边缘终止部分逐步减小的深度。
    • 5. 发明授权
    • Semiconductor device having a junction of P type pillar region and N type pillar region
    • 具有P型支柱区域和N型支柱区域的结的半导体器件
    • US08013360B2
    • 2011-09-06
    • US12764763
    • 2010-04-21
    • Wataru SaitoSyotaro OnoMasakatsu TakashitaYasuto SumiMasaru IzumisawaHiroshi OhtaWataru Sekine
    • Wataru SaitoSyotaro OnoMasakatsu TakashitaYasuto SumiMasaru IzumisawaHiroshi OhtaWataru Sekine
    • H01L29/66
    • H01L29/872H01L29/0619H01L29/0623H01L29/0634H01L29/0696H01L29/0878H01L29/402H01L29/404H01L29/41741H01L29/7395H01L29/7397H01L29/7722H01L29/7806H01L29/7811H01L29/8611
    • A semiconductor device includes: a semiconductor layer of a first conductivity type; a first semiconductor pillar region of the first conductivity type provided on a major surface of the semiconductor layer; a second semiconductor pillar region of a second conductivity type provided adjacent to the first semiconductor pillar region on the major surface of the semiconductor layer, the second semiconductor pillar region forming a periodic arrangement structure substantially parallel to the major surface of the semiconductor layer together with the first semiconductor pillar region; a first main electrode; a first semiconductor region of the second conductivity type; a second semiconductor region of the first conductivity type; a second main electrode; a control electrode; and a high-resistance semiconductor layer provided on the semiconductor layer in an edge termination section surrounding the first semiconductor pillar region and the second semiconductor pillar region. The high-resistance semiconductor layer has a lower dopant concentration than the first semiconductor pillar region. A boundary region is provided between a device central region and the edge termination section. The first semiconductor pillar region and the second semiconductor pillar region adjacent to the high-resistance semiconductor layer in the boundary region have a depth decreasing stepwise toward the edge termination section.
    • 半导体器件包括:第一导电类型的半导体层; 设置在半导体层的主表面上的第一导电类型的第一半导体柱区域; 第二导电类型的第二半导体柱区域,与半导体层的主表面上的第一半导体柱区域相邻设置,第二半导体柱区域形成基本上平行于半导体层的主表面的周期性排列结构以及 第一半导体柱区域; 第一主电极; 第二导电类型的第一半导体区域; 第一导电类型的第二半导体区域; 第二主电极; 控制电极; 以及设置在包围第一半导体柱区域和第二半导体柱区域的边缘终端部分的半导体层上的高电阻半导体层。 高电阻半导体层的掺杂浓度低于第一半导体柱区域。 边界区域设置在设备中心区域和边缘终端部分之间。 边界区域中与高电阻半导体层相邻的第一半导体柱区域和第二半导体柱区域具有沿着边缘终止部分逐步减小的深度。
    • 6. 发明申请
    • SEMICONDUCTOR DEVICE
    • 半导体器件
    • US20100200936A1
    • 2010-08-12
    • US12764763
    • 2010-04-21
    • Wataru SAITOSyotaro OnoMasakatsu TakashitaYasuto SumiMasaru IzumisawaHiroshi OhtaWataru Sekine
    • Wataru SAITOSyotaro OnoMasakatsu TakashitaYasuto SumiMasaru IzumisawaHiroshi OhtaWataru Sekine
    • H01L29/78
    • H01L29/872H01L29/0619H01L29/0623H01L29/0634H01L29/0696H01L29/0878H01L29/402H01L29/404H01L29/41741H01L29/7395H01L29/7397H01L29/7722H01L29/7806H01L29/7811H01L29/8611
    • A semiconductor device includes: a semiconductor layer of a first conductivity type; a first semiconductor pillar region of the first conductivity type provided on a major surface of the semiconductor layer; a second semiconductor pillar region of a second conductivity type provided adjacent to the first semiconductor pillar region on the major surface of the semiconductor layer, the second semiconductor pillar region forming a periodic arrangement structure substantially parallel to the major surface of the semiconductor layer together with the first semiconductor pillar region; a first main electrode; a first semiconductor region of the second conductivity type; a second semiconductor region of the first conductivity type; a second main electrode; a control electrode; and a high-resistance semiconductor layer provided on the semiconductor layer in an edge termination section surrounding the first semiconductor pillar region and the second semiconductor pillar region. The high-resistance semiconductor layer has a lower dopant concentration than the first semiconductor pillar region. A boundary region is provided between a device central region and the edge termination section. The first semiconductor pillar region and the second semiconductor pillar region adjacent to the high-resistance semiconductor layer in the boundary region have a depth decreasing stepwise toward the edge termination section.
    • 半导体器件包括:第一导电类型的半导体层; 设置在半导体层的主表面上的第一导电类型的第一半导体柱区域; 第二导电类型的第二半导体柱区域,与半导体层的主表面上的第一半导体柱区域相邻设置,第二半导体柱区域形成基本上平行于半导体层的主表面的周期性排列结构以及 第一半导体柱区域; 第一主电极; 第二导电类型的第一半导体区域; 第一导电类型的第二半导体区域; 第二主电极; 控制电极; 以及设置在包围第一半导体柱区域和第二半导体柱区域的边缘终端部分的半导体层上的高电阻半导体层。 高电阻半导体层的掺杂浓度低于第一半导体柱区域。 边界区域设置在设备中心区域和边缘终端部分之间。 边界区域中与高电阻半导体层相邻的第一半导体柱区域和第二半导体柱区域具有沿着边缘终止部分逐步减小的深度。
    • 7. 发明授权
    • Power semiconductor device
    • 功率半导体器件
    • US08283720B2
    • 2012-10-09
    • US12050415
    • 2008-03-18
    • Wataru SaitoSyotaro OnoMasakatsu TakashitaYauto SumiMasaru IzumisawaWataru SekineHiroshi OhtaShoichiro Kurushima
    • Wataru SaitoSyotaro OnoMasakatsu TakashitaYauto SumiMasaru IzumisawaWataru SekineHiroshi OhtaShoichiro Kurushima
    • H01L29/00H01L29/66
    • H01L29/7802H01L29/0634H01L29/0878H01L29/1095
    • A power semiconductor device includes: a first semiconductor layer; a second semiconductor layer and a third semiconductor layer provided in an upper portion of the first semiconductor layer and alternately arranged parallel to an upper surface of the first semiconductor layer; a plurality of fourth semiconductor layers provided on the third semiconductor layer; a fifth semiconductor layer selectively formed in an upper surface of each of the fourth semiconductor layers; a control electrode; a gate insulating film; a first main electrode provided on a lower surface of the first semiconductor layer; and a second main electrode provided on the fourth and the fifth semiconductor layers. Sum of the amount of impurities in the second semiconductor layer and the amount of impurities in the third semiconductor layer at an end on the second main electrode side of the second semiconductor layer and the third semiconductor layer is smaller than the sum at a center of the second semiconductor layer and the third semiconductor layer in the direction from the first main electrode to the second main electrode.
    • 功率半导体器件包括:第一半导体层; 第二半导体层和第三半导体层,设置在所述第一半导体层的上部并且交替地平行于所述第一半导体层的上表面布置; 设置在所述第三半导体层上的多个第四半导体层; 选择性地形成在每个第四半导体层的上表面中的第五半导体层; 控制电极; 栅极绝缘膜; 设置在所述第一半导体层的下表面上的第一主电极; 以及设置在第四和第五半导体层上的第二主电极。 第二半导体层中的杂质量和第二半导体层的第二主电极侧端部的第三半导体层中的杂质量的和小于第二半导体层的第二主电极侧的和 第二半导体层和第三半导体层在从第一主电极到第二主电极的方向上。
    • 8. 发明申请
    • POWER SEMICONDUCTOR DEVICE
    • 功率半导体器件
    • US20080246079A1
    • 2008-10-09
    • US12050415
    • 2008-03-18
    • Wataru SaitoSyotaro OnoMasakatsu TakashitaYauto SumiMasaru IzumisawaWataru SekineHiroshi OhtaShoichiro Kurushima
    • Wataru SaitoSyotaro OnoMasakatsu TakashitaYauto SumiMasaru IzumisawaWataru SekineHiroshi OhtaShoichiro Kurushima
    • H01L29/00
    • H01L29/7802H01L29/0634H01L29/0878H01L29/1095
    • A power semiconductor device includes: a first semiconductor layer; a second semiconductor layer and a third semiconductor layer provided in an upper portion of the first semiconductor layer and alternately arranged parallel to an upper surface of the first semiconductor layer; a plurality of fourth semiconductor layers provided on the third semiconductor layer; a fifth semiconductor layer selectively formed in an upper surface of each of the fourth semiconductor layers; a control electrode; a gate insulating film; a first main electrode provided on a lower surface of the first semiconductor layer; and a second main electrode provided on the fourth and the fifth semiconductor layers. Sum of the amount of impurities in the second semiconductor layer and the amount of impurities in the third semiconductor layer at an end on the second main electrode side of the second semiconductor layer and the third semiconductor layer is smaller than the sum at a center of the second semiconductor layer and the third semiconductor layer in the direction from the first main electrode to the second main electrode.
    • 功率半导体器件包括:第一半导体层; 第二半导体层和第三半导体层,设置在所述第一半导体层的上部并且交替地平行于所述第一半导体层的上表面布置; 设置在所述第三半导体层上的多个第四半导体层; 选择性地形成在每个第四半导体层的上表面中的第五半导体层; 控制电极; 栅极绝缘膜; 设置在所述第一半导体层的下表面上的第一主电极; 以及设置在第四和第五半导体层上的第二主电极。 第二半导体层中的杂质量和第二半导体层的第二主电极侧端部的第三半导体层中的杂质量的和小于第二半导体层的第二主电极侧的和 第二半导体层和第三半导体层在从第一主电极到第二主电极的方向上。