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1. 发明授权

US06728651B1 Methods and apparatuses for digitally tuning a phased-lock loop circuit 有权
标题翻译：用于数字调谐锁相环电路的方法和装置
公开(公告)号：US06728651B1
公开(公告)日：2004-04-27
申请号：US10097904
申请日：2002-03-13
申请人： Tim Alton , Wai-Kong Chen , Michael Davis , Warren Necoechea
发明人： Tim Alton , Wai-Kong Chen , Michael Davis , Warren Necoechea
IPC分类号： G06F1900
CPC分类号： H03L7/085
摘要： A phase-locked loop circuit having a programmable tuning voltage. As the input reference clock frequency is changed, the tuning voltage is changed accordingly to compensate for the propagation delay through the phase detector and thereby reduce discrepancies in the phase relationship between the input reference clock signal and the output clock signal at different frequencies. A set of compensation values corresponding to input reference clock frequencies are stored in a memory device. When the input reference clock frequency is changed, a corresponding compensation value is programmed to a digital-to-analog converter (DAC). The DAC outputs a voltage that is proportional to the value of the digital input to the DAC and can thus be used to regulate the tuning voltage of the PLL circuit so that the relationship of the input reference clock signal to the output clock signal remains stable with frequency changes.
摘要翻译：具有可编程调谐电压的锁相环电路。随着输入参考时钟频率的改变，调谐电压相应地被改变以补偿通过相位检测器的传播延迟，从而减少输入参考时钟信号和不同频率处的输出时钟信号之间的相位关系的差异。对应于输入参考时钟频率的一组补偿值被存储在存储器件中。当输入参考时钟频率改变时，相应的补偿值被编程到数模转换器（DAC）。 DAC输出与DAC的数字输入值成比例的电压，因此可用于调节PLL电路的调谐电压，使得输入参考时钟信号与输出时钟信号的关系保持稳定，频率变化。

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