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    • 1. 发明授权
    • Stacked double balanced mixer circuit
    • 堆叠双平衡混频器电路
    • US5448772A
    • 1995-09-05
    • US297072
    • 1994-08-29
    • Walter J. Grandfield
    • Walter J. Grandfield
    • H03C1/54H03D7/12H03D7/14H03D7/16H04B1/28H03B19/00
    • H03D7/1425H03D7/1433H03D7/1458H03D7/165H03C1/542H03D2200/0019H03D2200/0025H03D2200/0043H03D2200/0084H03D2200/0088H03D7/125
    • A stacked double balanced mixer (220) includes a double balanced mixer (320) and a first cross coupled differential mixer (330). The double balanced mixer (320) includes two input transistors (321, 322) and four cross coupled output transistors (323-326). The first cross coupled differential mixer (330) includes four cross coupled input/output transistors (331-334) and a second mixer output (227, 228). The four cross coupled input/output transistors (331-334) have first output terminal pairs DC coupled in series to second output terminal pairs of the four cross coupled output transistors (323-326). The stacked double balanced mixer (220) generates, at the second mixer output (227,228), a second IF differential output signal having a second IF frequency at a difference of a radio frequency of a differential input signal and the sum of first and second LO frequencies, respectively, of first and second LO signals.
    • 叠层双平衡混合器(220)包括双平衡混合器(320)和第一交叉耦合差分混合器(330)。 双平衡混频器(320)包括两个输入晶体管(321,322)和四个交叉耦合的输出晶体管(323-326)。 第一交叉耦合差分混频器(330)包括四个交叉耦合的输入/输出晶体管(331-334)和第二混频器输出(227,228)。 四个交叉耦合输入/输出晶体管(331-334)具有串联连接到四个交叉耦合输出晶体管(323-326)的第二输出端子对的第一输出端子对。 堆叠双平衡混频器(220)在第二混频器输出(227,228)处产生第二IF差分输出信号,该第二IF差分输出信号具有差分输入信号的射频的差和第一和第二LO的和的第二IF频率 频率分别为第一和第二LO信号。
    • 3. 发明授权
    • Constant propagation delay current reference
    • 恒定传播延迟电流参考
    • US4862015A
    • 1989-08-29
    • US163909
    • 1988-03-03
    • Walter J. Grandfield
    • Walter J. Grandfield
    • G05F1/46H03K3/03H03L7/099
    • H03L7/0805G05F1/466H03K3/0315H03L7/0995
    • A constant propagation delay current reference is provided having an external source providing a reference frequency signal. A phase lock loop is provided which is responsive to the reference frequency signal and to an operating frequency signal to provide a current reference signal at the output of the loop. The current reference signal is provided to a current to frequency converter which generates the operating frequency signal. A current mirror, also coupled to the phase lock loop output provides an output current proportional to the current reference signal which is suitable for providing the injector current for I.sup.2 L devices. The output current tracks the process, voltage and temperature variations of the integrated circuit, allowing the injector currents to be optimized for maintaining constant propagation delay in the circuits being powered.
    • 提供了具有提供参考频率信号的外部源的恒定传播延迟电流参考。 提供了一个锁相环,其响应于参考频率信号和工作频率信号,以在环路的输出处提供电流参考信号。 电流参考信号被提供给产生工作频率信号的电流到频率转换器。 还耦合到锁相环输出的电流镜提供与当前参考信号成比例的输出电流,其适于为I2L器件提供注射器电流。 输出电流跟踪集成电路的过程,电压和温度变化,允许喷射器电流被优化,以便在被供电的电路中保持恒定的传播延迟。
    • 5. 发明授权
    • Paging terminal apparatus with page forwarding capability and
methodology thereof
    • 具有页面转发能力及其方法的寻呼终端设备
    • US4814763A
    • 1989-03-21
    • US132825
    • 1987-12-14
    • Leonard E. NelsonVictoria A. LeonardoWalter J. Grandfield
    • Leonard E. NelsonVictoria A. LeonardoWalter J. Grandfield
    • H04W88/18H04Q7/00
    • H04W88/185
    • Apparatus and method is disclosed for automatically, or by selective response, call forwarding a message to one or more system pagers which have an acknowledge back capability.In one embodiment, disclosed apparatus automatically forwards a message to another system pager upon the initially called pager failing to acknowledge back within a predetermined time period. Such other pager is determined from a set paging hierarchy included within the paging terminal apparatus itself.In another embodiment, wherein the system pagers have multiple acknowledge back response capability, a called pager can request the received message be additionally call forwarded to one or more other system pagers in accordance with the particular acknowledge back response chosen by the called pager user.
    • 公开了一种装置和方法,用于自动或通过选择性响应将消息呼叫转发给具有应答能力的一个或多个系统寻呼机。 在一个实施例中,所公开的设备在初始调用的寻呼机在预定时间段内未能确认回来时,自动地将消息转发到另一个系统寻呼机。 这种其他寻呼机是从包含在寻呼终端设备本身内的一组寻呼层级确定的。 在另一个实施例中,其中系统寻呼机具有多个确认回应能力,被呼叫的寻呼机可以根据被叫寻呼机用户所选择的特定应答响应来另外呼叫被转接到一个或多个其它系统寻呼机。
    • 8. 发明授权
    • Pager receiver having a common timer circuit for both sequential
lock-out and out-of-range
    • 寻呼机接收机具有用于顺序锁定和超出范围的公共定时器电路
    • US4928086A
    • 1990-05-22
    • US302876
    • 1989-01-30
    • George DrapacWalter J. Grandfield
    • George DrapacWalter J. Grandfield
    • G08B3/10H04W88/02
    • H04W88/026G08B3/1066
    • A pager receiver includes at least one lock-out circuit, an out-of range circuit, and a single timer coupled to the lock-out and out-of range circuits and responsive to timing signals generated by the pager for generating an initiated one of either the lock-out timer interval or out-of range time interval. Each lock-out circuit of the pager receiver corresponds to an address function programmed therein and is activated by the function detect signal generated in response to the initial decoding of the corresponding address function to initiate the generation of the lock-out time interval by the single timer and to inhibit the corresponding alert annunciation from responding to subsequently generated function detect signals corresponding thereto for the duration of the lock-out time interval. The single timer is also initiated to generate the out-of-range time interval at the generation of each sync pulse timing signal by the pager receiver, but only in the absence of an activated lock-out circuit. Accordingly, the single timer is disabled from initiating the generation of the out-of-range time interval for the duration of an initiated lock-out time interval. Still further, the single timer may be reinitiated to generate the lock-out time interval during the generation of a lock-out time interval by an activated lock-out circuit corresponding to an uninhibited alert annunciation.
    • 寻呼机接收机包括至少一个锁定电路,超出范围电路和耦合到锁定和超出范围电路的单个定时器,并且响应于由寻呼机产生的定时信号,用于产生发起的一个 锁定定时器间隔或超出范围时间间隔。 寻呼机接收机的每个锁定电路对应于其中编程的地址功能,并且由响应于相应地址功能的初始解码而产生的功能检测信号激活,以启动由单个接收器产生锁定时间间隔 定时器,并且在锁定时间间隔的持续时间内禁止相应的警报通知响应随后产生的对应于其的功能检测信号。 单个定时器也被启动以在寻呼机接收机产生每个同步脉冲定时信号时产生超出时间间隔,但是仅在没有激活的锁定电路的情况下才产生。 因此,在启动的锁定时间间隔期间,单个定时器被禁止发起超出范围时间间隔的生成。 此外,可以通过对应于不受限制的警报通知的激活的锁定电路来重新启动单个定时器以在生成锁定时间间隔期间产生锁定时间间隔。