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标题翻译： WAFER-LEVEL芯片尺寸包装及其制造和使用方法

公开(公告)号：WO2005008724A2

公开(公告)日：2005-01-27

申请号：PCT/US2004021940

申请日：2004-07-08

申请人： FAIRCHILD SEMICONDUCTOR , JOSHI RAJEEV , WU CHUNG-LI , LEE SANG-DO , CHOI YOON-HWA , PARK MIN-HYO , KIM JI-HWAN

发明人： JOSHI RAJEEV , WU CHUNG-LI , LEE SANG-DO , CHOI YOON-HWA , PARK MIN-HYO , KIM JI-HWAN

IPC分类号： H01L21/60 , H01L21/68 , H01L23/31 , H01L23/485 , H01L23/525 , H01L

CPC分类号： H01L21/6835 , H01L21/568 , H01L23/3114 , H01L23/3171 , H01L23/525 , H01L24/11 , H01L24/13 , H01L24/29 , H01L24/83 , H01L24/97 , H01L2224/0231 , H01L2224/0401 , H01L2224/05624 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05671 , H01L2224/11 , H01L2224/1134 , H01L2224/13 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2224/16225 , H01L2224/29101 , H01L2224/2919 , H01L2224/29399 , H01L2224/32225 , H01L2224/73104 , H01L2224/73204 , H01L2224/838 , H01L2224/97 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/0781 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/1461 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/351 , H01L2224/81 , H01L2924/00014 , H01L2224/13099 , H01L2924/00 , H01L2924/01023 , H01L2924/01028 , H01L2924/3512

摘要： First, second, and third packaged semiconductor devices (a wafer-level chip scale package) are described. The first packaged semiconductor device contains no UBM between a chip pad and an RDL pattern. The first device contains only a single non-polymeric insulation layer between the RDL pattern and the solder bump, where the insulation layer does not need high temperature curing processes and so does not induce thermal stresses into the device. Manufacturing costs for the first device are diminished by eliminating the UBM between the chip pad and the RDL pattern. The second packaged semiconductor device (a second wafer-level chip scale package) contains an adhesive film containing conductive particles sandwiched between a chip with Cu-based stud bumps and a substrate containing a bond pad. Some conductive particles are sandwiched between the stud bump and bond pad to create a conductive path. The second device is manufactured without the steps of dispensing solder and reflowing the solder and can optionally eliminate the use of a redistribution trace. Using such a configuration increases the reliability of the second wafer-level chip scale package. The third packaged semiconductor device (a third wafer-level chip scale package) contains a conductive adhesive material as an electrical interconnect route between the semiconductor die and a patterned conductive substrate. The patterned conductive substrate acts not only as a substrate, but also as a redistribution layer that converts the dense pad layout of the die to a larger array configuration of the solder balls in the circuit board. Using the invention allows the formation of a lower priced chip scale package that overcomes the restriction of the die size used in die-sized chip packages and the input-output pattern that can be required by the printed circuit board. Thus, the invention can provide a familiar pitch (i.e., interface) to the printed circuit board for any small die.

摘要翻译：第一，第二和第三封装半导体器件（晶片级芯片级封装）被描述。第一封装半导体器件在芯片焊盘和RDL图案之间不包含UBM。第一器件在RDL图案和焊料凸块之间仅包含单个非聚合物绝缘层，其中绝缘层不需要高温固化工艺，因此不会将热应力引入器件。通过消除芯片焊盘和RDL图案之间的UBM，可以减少第一个器件的制造成本。第二封装半导体器件（第二晶片级芯片级封装）包含夹有包含Cu基柱凸块的芯片和含有焊盘的衬底的导电颗粒的粘合膜。一些导电颗粒被夹在柱形凸块和接合垫之间以产生导电路径。制造第二装置不需要分配焊料和回流焊料的步骤，并且可以可选地消除再分布迹线的使用。使用这种配置增加了第二晶片级芯片级封装的可靠性。第三封装半导体器件（第三晶片级芯片级封装）包含作为半导体管芯和图案化导电衬底之间的电互连路径的导电粘合剂材料。图案化导电衬底不仅用作衬底，而且还用作将芯片的致密衬垫布局转换成电路板中的焊球的更大阵列配置的再分配层。使用本发明允许形成较低价格的芯片级封装，其克服了芯片尺寸芯片封装中使用的裸片尺寸的限制以及印刷电路板可能需要的输入 - 输出图案。因此，本发明可以为任何小型芯片提供与印刷电路板的熟悉的间距（即接口）。

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