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1. 发明专利

AU1166901A Apparatus for attaching resists and wafers to substrates 未知
公开(公告)号：AU1166901A
公开(公告)日：2001-04-30
申请号：AU1166901
申请日：2000-10-12
申请人： GEN SEMICONDUCTOR OF TAIWAN LT , WILLIAM JOHN NELSON , STANLEY LAI , LARRY SHEN , JACK LIN , SHYAN I WU WU
发明人： NELSON WILLIAM JOHN , LAI STANLEY , SHEN LARRY , LIN JACK , WU SHYAN-I WU
IPC分类号： H01L21/00

2. 发明授权

US06657255B2 Trench DMOS device with improved drain contact 有权
标题翻译：沟槽DMOS器件具有改善的漏极接触
公开(公告)号：US06657255B2
公开(公告)日：2003-12-02
申请号：US10021419
申请日：2001-10-30
申请人： Fwu-Iuan Hshieh , Koon Chong So , William John Nelson , John E. Amato
发明人： Fwu-Iuan Hshieh , Koon Chong So , William John Nelson , John E. Amato
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L29/0653 , H01L29/41741 , H01L29/41766 , H01L29/7809 , H01L29/7811
摘要： A trench DMOS transistor device that comprises: (a) a substrate of a first conductivity type; (b) an epitaxial layer of first conductivity type over the substrate, wherein the epitaxial layer has a lower majority carrier concentration than the substrate; (c) a trench extending into the epitaxial layer from an upper surface of the epitaxial layer; (d) an insulating layer lining at least a portion of the trench; (e) a conductive region within the trench adjacent the insulating layer; (f) a body region of a second conductivity type provided within an upper portion of the epitaxial layer and adjacent the trench; (g) a source region of first conductivity type within an upper portion of the body region and adjacent the trench; and (h) one or more low resistivity deep regions extending into the device from an upper surface of the epitaxial layer. The low resistivity deep region acts to provide electrical contact with the substrate, which is a common drain region for the device. By constructing a trench DMOS transistor device in this fashion, source, drain and gate contacts can all be provided on a single surface of the device.
摘要翻译：一种沟槽DMOS晶体管器件，其包括：（a）第一导电类型的衬底; （b）在所述衬底上的第一导电类型的外延层，其中所述外延层具有比所述衬底更低的载流子浓度; （c）从外延层的上表面延伸到外延层中的沟槽; （d）衬在所述沟槽的至少一部分上的绝缘层; （e）邻近绝缘层的沟槽内的导电区域; （f）设置在所述外延层的上部并且与所述沟槽相邻的第二导电类型的体区; （g）第一导电类型的源区域，位于本体区域的上部并且与沟槽相邻; 和（h）从外延层的上表面延伸到器件中的一个或多个低电阻率深区域。低电阻率深区用于与衬底电接触，衬底是衬底的共用漏极区。通过以这种方式构造沟槽DMOS晶体管器件，源极，漏极和栅极触点都可以设置在器件的单个表面上。

3. 发明授权

US06291316B1 Method for fabricating passivated semiconductor devices 有权
标题翻译：钝化半导体器件的制造方法
公开(公告)号：US06291316B1
公开(公告)日：2001-09-18
申请号：US09233706
申请日：1999-01-19
申请人： Christopher Michael Knowles , Yih-Yin Lin , Tung-Chieh Lin , William John Nelson , Hung-Ping Tsai , Richard Sean O'Rourke
发明人： Christopher Michael Knowles , Yih-Yin Lin , Tung-Chieh Lin , William John Nelson , Hung-Ping Tsai , Richard Sean O'Rourke
IPC分类号： H01L2146
CPC分类号： H01L23/3178 , H01L21/76224 , H01L2924/0002 , Y10S438/958 , H01L2924/00
摘要： A wafer-level process for fabricating a plurality of passivated semiconductor devices comprising the steps of providing a semiconductor wafer on that at least one p-n junction is formed, Cutting a plurality of grooves in said wafer to expose said at least one p-n junction, wherein each of said grooves extends partly through the wafer and has a depth that is enough to expose said at least one p-n junction, applying a passivating material into said grooves and curing the material. The grooves can be formed by using a disc saw having a blade, by performing a sandblasting operation within a controlled operation time, or by performing a photolithographically chemical etching process. The passivating material is either screen-printed or pin-dispensed into the grooves. A dicing operation can be subsequently proceeded to divide the wafer into individual chips for subsequent fabrication into completed semiconductor devices.
摘要翻译：一种用于制造多个钝化半导体器件的晶片级工艺，包括以下步骤：在该至少一个pn结上提供半导体晶片;在所述晶片中切割多个凹槽以暴露所述至少一个pn结，其中每个所述凹槽部分地延伸穿过晶片并且具有足以露出所述至少一个pn结的深度，将钝化材料施加到所述凹槽中并固化材料。可以通过使用具有叶片的盘锯，通过在受控的操作时间内进行喷砂操作，或通过进行光刻化学蚀刻工艺来形成凹槽。钝化材料被丝网印刷或销钉分配到凹槽中。随后可以进行切割操作以将晶片分成单个芯片，以便随后制造成完整的半导体器件。

4. 发明授权

US07049194B2 Trench DMOS device with improved drain contact 有权
公开(公告)号：US07049194B2
公开(公告)日：2006-05-23
申请号：US10725326
申请日：2003-12-01
申请人： Fwu-Iuan Hshieh , Koon Chong So , William John Nelson , John E. Amato
发明人： Fwu-Iuan Hshieh , Koon Chong So , William John Nelson , John E. Amato
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/0653 , H01L29/41741 , H01L29/41766 , H01L29/7809 , H01L29/7811
摘要： A trench DMOS transistor device that comprises: (a) a substrate of a first conductivity type; (b) an epitaxial layer of first conductivity type over the substrate, wherein the epitaxial layer has a lower majority carrier concentration than the substrate; (c) a trench extending into the epitaxial layer from an upper surface of the epitaxial layer; (d) an insulating layer lining at least a portion of the trench; (e) a conductive region within the trench adjacent the insulating layer; (f) a body region of a second conductivity type provided within an upper portion of the epitaxial layer and adjacent the trench; (g) a source region of first conductivity type within an upper portion of the body region and adjacent the trench; and (h) one or more low resistivity deep regions extending into the device from an upper surface of the epitaxial layer. The low resistivity deep region acts to provide electrical contact with the substrate, which is a common drain region for the device. By constructing a trench DMOS transistor device in this fashion, source, drain and gate contacts can all be provided on a single surface of the device.

5. 发明授权

US06712110B1 Apparatus for attaching resists and wafers to substrates 有权
标题翻译：用于将抗蚀剂和晶片附着到基底上的装置
公开(公告)号：US06712110B1
公开(公告)日：2004-03-30
申请号：US10110495
申请日：2002-09-23
申请人： William John Nelson , Stanley Lai , Larry Shen , Jack Lin , Shyan-I Wu
发明人： William John Nelson , Stanley Lai , Larry Shen , Jack Lin , Shyan-I Wu
IPC分类号： B32B3100
CPC分类号： H01L21/6715 , H01L21/67132 , Y10T156/1744 , Y10T156/1798
摘要： This invention is related to an apparatus for attaching resists and wafers to substrates, including: first and a second moving devices for moving substrates and wafers respectively; a first tank for containing an adhesive agent; a dispensing device which dispenses a predetermined amount of the adhesive agent at the central region of the wafer; a third moving device for placing the substrate on the wafer, a compressing device which compresses the substrate to squeeze out any possible air bubble existing within the adhesive agent between the substrate and the wafer; a second tank for containing the adhesive agent; a fourth moving device for moving the attached substrate and the wafer together to the second tank such that the complete area of the wafer at the side thereof opposite to the substrate is covered with the adhesive agent in an appropriate amount; a mold having a plurality of cavities arranged in a required pattern; a supplying device for providing a plurality of resists on the mold; a shake-and-load device which shakes the mold such that the resists may be positioned into the cavities thereof; an adherent tape for adhering the resists which are arranged in accordance with the pattern of the mold; the fourth moving device to move the substrate and the wafer together onto the resists and the adherent tape such that the resists are attached with the wafer by the adhesive agent thereon; and a wrapping device for moving the adherent tape and separating the adherent tape from the resists.
摘要翻译：本发明涉及一种用于将抗蚀剂和晶片附着于基底的装置，包括：分别用于移动基底和晶片的第一和第二移动装置; 用于容纳粘合剂的第一罐; 分配装置，其在晶片的中心区域分配预定量的粘合剂; 用于将基板放置在晶片上的第三移动装置，压缩装置，其压缩基板以挤出存在于基板和晶片之间的粘合剂内的任何可能的气泡; 用于容纳粘合剂的第二罐; 用于将连接的基板和晶片一起移动到第二槽的第四移动装置，使得在与基板相对的一侧的晶片的整个区域以适当的量被粘合剂覆盖; 具有以所需图案排列的多个空腔的模具; 用于在模具上提供多个抗蚀剂的供应装置; 摇动和负载装置，其使模具摇动，使得抗蚀剂可以定位到其空腔中; 用于粘附根据模具图案布置的抗蚀剂的粘合带; 所述第四移动装置将所述基板和所述晶片一起移动到所述抗蚀剂和所述粘合带上，使得所述抗蚀剂通过所述粘合剂在所述晶片上附着在其上; 以及用于移动粘附带并将粘附带与抗蚀剂分离的包装装置。

6. 发明授权

US06395982B1 Leaded semiconductor device package for use in nonsoldering assembling 有权
公开(公告)号：US06395982B1
公开(公告)日：2002-05-28
申请号：US09209345
申请日：1998-12-11
申请人： William John Nelson , Alice Tseng , K. R. Lee , Stanley Lai
发明人： William John Nelson , Alice Tseng , K. R. Lee , Stanley Lai
IPC分类号： H01L2302
摘要： A leaded semiconductor device package for nonsoldering assembling is disclosed. In the package of the invention, both leads of a semiconductor device package are flattened, cut and bent by automatic machines on the bais of conventional packaging process. Unlike a conventional semiconductor device package which is electrically connected to a circuit by soldering, the flattened and bent parts of both leads of the semiconductor device package can be electrically connected to a circuit by elastically contacting and directly assembling without soldering.

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