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1. 发明申请

WO2011143527A2 PROCESS KIT SHIELD FOR IMPROVED PARTICLE REDUCTION 审中-公开
标题翻译：用于改善颗粒减少的工艺套件
公开(公告)号：WO2011143527A2
公开(公告)日：2011-11-17
申请号：PCT/US2011036395
申请日：2011-05-13
申请人： APPLIED MATERIALS INC , RASHEED MUHAMMAD , WANG RONGJUN , LIU ZHENDONG , FU XINYU , TANG XIANMIN
发明人： RASHEED MUHAMMAD , WANG RONGJUN , LIU ZHENDONG , FU XINYU , TANG XIANMIN
IPC分类号： C23C14/34 , C23C14/06
CPC分类号： C23C14/35 , C23C14/564 , H01J37/32853 , H01J37/32871 , H01J37/34 , H01J37/3411
摘要： Apparatus for improved particle reduction are provided herein. In some embodiments, an apparatus may include a process kit shield comprising a one-piece metal body having an upper portion and a lower portion and having an opening disposed through the one-piece metal body, wherein the upper portion includes an opening-facing surface configured to be disposed about and spaced apart from a target of a physical vapor deposition chamber and wherein the opening-facing surface is configured to limit particle deposition on an upper surface of the upper portion of the one-piece metal body during sputtering of a target material from the target of the physical vapor deposition chamber.
摘要翻译：本文提供了用于改善颗粒减少的装置。在一些实施例中，一种装置可以包括一个包括具有上部和下部的一体式金属体的处理套件屏蔽件，并且具有穿过一体式金属体设置的开口，其中，上部包括面向开口的表面被配置为围绕物理气相沉积室的目标设置并隔开，并且其中所述面向开口的表面构造成在目标溅射期间限制所述一体金属体的上部的上表面上的颗粒沉积材料从物理气相沉积室的目标。

2. 发明申请

WO2010114823A2 SPUTTERING TARGET FOR PVD CHAMBER 审中-公开
标题翻译： PVD室的喷射目标
公开(公告)号：WO2010114823A2
公开(公告)日：2010-10-07
申请号：PCT/US2010029171
申请日：2010-03-30
申请人： APPLIED MATERIALS INC , LIU ZHENDONG , WANG RONGJUN , TANG XIANMIN , GANDIKOTA SRINIVAS , GUNG TZA-JING , RASHEED MUHAMMAD M
发明人： LIU ZHENDONG , WANG RONGJUN , TANG XIANMIN , GANDIKOTA SRINIVAS , GUNG TZA-JING , RASHEED MUHAMMAD M
IPC分类号： H01L21/203 , C23C14/34
CPC分类号： C23C14/3407 , H01J37/342 , H01J37/3423
摘要： Target assemblies and PVD chambers including target assemblies are disclosed. The target assembly includes a target that has a concave shaped target. When used in a PVD chamber, the concave target provides more radially uniform deposition on a substrate disposed in the sputtering chamber.
摘要翻译：公开了包括目标组件的目标组件和PVD室。目标组件包括具有凹形目标的目标。当在PVD室中使用时，凹目标在设置在溅射室中的基板上提供更径向均匀的沉积。

3. 发明申请

WO2008027186A2 INTEGRATED PROCESS FOR SPUTTER DEPOSITION OF A CONDUCTIVE BARRIER LAYER, ESPECIALLY AN ALLOY OF RUTHENIUM AND TANTALUM, UNDERLYING COPPER OR COPPER ALLOY SEED LAYER 审中-公开
标题翻译：导电阻挡层溅射沉积的综合工艺，特别是铜和钽的合金，铜或铜合金层
公开(公告)号：WO2008027186A2
公开(公告)日：2008-03-06
申请号：PCT/US2007017967
申请日：2007-08-14
申请人： APPLIED MATERIALS INC , WANG RONGJUN , CHUNG HUA , TANG XIANMIN , WANG JENN YUE , WANG WEI D , TANAKA YOICHIRO , YU JICK M , GOPALRAJA PRABURAM
发明人： WANG RONGJUN , CHUNG HUA , TANG XIANMIN , WANG JENN YUE , WANG WEI D , TANAKA YOICHIRO , YU JICK M , GOPALRAJA PRABURAM
IPC分类号： B32B7/00 , B05D5/12 , B32B3/00 , C23C14/00 , C23C16/00
CPC分类号： C23C14/046 , C23C14/0641 , C23C14/165 , H01L21/2855 , H01L21/76844 , H01L21/76846 , H01L21/76873 , H01L23/53238 , H01L2924/0002 , Y10T428/24917 , Y10T428/24926 , H01L2924/00
摘要： A fabrication method and a product for the deposition of a conductive barrier or other liner layer in a vertical electrical interconnect structure. One embodiment includes within a hole (88) through a dielectric layer (86) a barrier layer (132) of RuTaN, an adhesion layer (112) of RuTa, and a copper seed layer (114) forming a liner for electroplating of copper. The ruthenium content is preferably greater than 50 at% and more preferably at least 80 at% but less than 95 at%. The barrier and adhesion layers may both be sputter deposited. Other platinum-group elements substitute for the ruthenium and other refractory metals substitute for the tantalum. Aluminum alloying into RuTa (192, 194) when annealed presents a moisture barrier. Copper contacts (232, 238) include different alloying fractions of RuTa to shift the work function to the doping type of the silicon (216, 218).
摘要翻译：用于在垂直电互连结构中沉积导电屏障或其它衬垫层的制造方法和产品。一个实施例包括穿过介电层（86）的孔（88）中的RuTaN的阻挡层（132），RuTa的粘合层（112）和形成铜电镀衬垫的铜籽晶层（114）。钌含量优选大于50原子％，更优选至少80原子％但小于95原子％。阻挡层和粘附层可以被溅射沉积。其他铂族元素代替钌和其他难熔金属代替钽。当退火时，铝合金化成RuTa（192,194）具有防潮层。铜触点（232,238）包括RuTa的不同合金分数，以将功函数移动到硅的掺杂类型（216,218）。

4. 发明申请

WO2014008162A1 ALUMINUM-NITRIDE BUFFER AND ACTIVE LAYERS BY PHYSICAL VAPOR DEPOSITION 审中-公开
标题翻译：铝 - 氮化物缓冲层和活性层通过物理蒸气沉积
公开(公告)号：WO2014008162A1
公开(公告)日：2014-01-09
申请号：PCT/US2013/048879
申请日：2013-07-01
申请人： APPLIED MATERIALS, INC. , ZHU, Mingwei , PATIBANDLA, Nag B. , WANG, Rongjun , AGRAWAL, Vivek , SUBRAMANI, Anantha , DIEHL, Daniel L. , TANG, Xianmin
发明人： ZHU, Mingwei , PATIBANDLA, Nag B. , WANG, Rongjun , AGRAWAL, Vivek , SUBRAMANI, Anantha , DIEHL, Daniel L. , TANG, Xianmin
IPC分类号： C23C14/34 , C23C14/06 , C23C14/54
CPC分类号： H01L21/0254 , C23C14/0036 , C23C14/0641 , H01J37/3426 , H01J37/3467 , H01L21/02458 , H01L21/02631 , H01L21/3065 , H01L21/3228
摘要： Embodiments of the invention described herein generally relate to an apparatus and methods for forming high quality buffer layers and Group III-V layers that are used to form a useful semiconductor device, such as a power device, light emitting diode (LED), laser diode (LD) or other useful device. Embodiments of the invention may also include an apparatus and methods for forming high quality buffer layers, Group III-V layers and electrode layers that are used to form a useful semiconductor device. In some embodiments, an apparatus and method includes the use of one or more cluster tools having one or more physical vapor deposition (PVD) chambers that are adapted to deposit a high quality aluminum nitride (AlN) buffer layer that has a high crystalline orientation on a surface of a plurality of substrates at the same time.
摘要翻译：本文描述的本发明的实施例一般涉及用于形成高质量缓冲层的装置和方法，以及用于形成有用的半导体器件的III-V层，例如功率器件，发光二极管（LED），激光二极管（LD）或其他有用的装置。本发明的实施例还可以包括用于形成用于形成有用的半导体器件的高质量缓冲层，III-V族层和电极层的装置和方法。在一些实施例中，装置和方法包括使用具有一个或多个物理气相沉积（PVD）室的一个或多个簇工具，其适于将具有高结晶取向的高质量氮化铝（AlN）缓冲层沉积在同时是多个基板的表面。

5. 发明申请

WO2012109069A3 PVD SPUTTERING TARGET WITH A PROTECTED BACKING PLATE 审中-公开
标题翻译：带有保护背板的PVD溅射目标
公开(公告)号：WO2012109069A3
公开(公告)日：2013-01-03
申请号：PCT/US2012023474
申请日：2012-02-01
申请人： APPLIED MATERIALS INC , RASHEED MUHAMMAD M , WANG RONGJUN
发明人： RASHEED MUHAMMAD M , WANG RONGJUN
IPC分类号： C23C14/34 , C23C14/50
CPC分类号： C23C14/3407 , C22C9/00 , C22C9/04 , C22C19/03 , C23C14/3414 , H01J37/3426 , H01J37/3435
摘要： Embodiments of the invention provide sputtering targets utilized in physical vapor deposition (PVD) and methods to form such sputtering targets. In one embodiment, a sputtering target contains a target layer disposed on a backing plate, and a protective coating layer - usually containing a nickel material - covering and protecting a region of the backing plate that would otherwise be exposed to plasma during the PVD processes. In many examples, the target layer contains a nickel-platinum alloy, the backing plate contains a copper alloy (e.g., copper-zinc), and the protective coating layer contains metallic nickel. The protective coating layer eliminates the formation of highly conductive, copper contaminants typically derived by plasma erosion of the copper alloy contained within the exposed surfaces of the backing plate. Therefore, the substrates and the interior surfaces of the PVD chamber remain free of such copper contaminants during the PVD processes.
摘要翻译：本发明的实施例提供了用于物理气相沉积（PVD）的溅射靶和形成这种溅射靶的方法。在一个实施例中，溅射靶包含设置在背板上的目标层和通常包含镍材料的保护涂层 - 覆盖并保护背衬板的区域，否则在PVD工艺期间将暴露于等离子体。在许多实施例中，靶层含有镍 - 铂合金，背板含有铜合金（例如铜 - 锌），保护涂层含有金属镍。保护涂层消除了形成高度导电的铜污染物，通常由包含在背板的暴露表面内的铜合金的等离子体侵蚀导致。因此，在PVD工艺期间，PVD室的基板和内表面保持没有这种铜污染物。

6. 发明申请

WO2011019566A2 PROCESS KIT FOR RF PHYSICAL VAPOR DEPOSITION 审中-公开
标题翻译： RF物理蒸气沉积工艺套件
公开(公告)号：WO2011019566A2
公开(公告)日：2011-02-17
申请号：PCT/US2010/044420
申请日：2010-08-04
申请人： APPLIED MATERIALS, INC. , HAWRYLCHAK, Lara , SAVANDAIAH, Kirankumar , RASHEED, Muhammad, M. , WANG, Rongjun , ALLEN, Adolph, Miller , XIE, Zhigang
发明人： HAWRYLCHAK, Lara , SAVANDAIAH, Kirankumar , RASHEED, Muhammad, M. , WANG, Rongjun , ALLEN, Adolph, Miller , XIE, Zhigang
IPC分类号： H01L21/203 , C23C14/34
CPC分类号： H01L21/67017 , C23C14/34 , C23C14/564 , H01J37/3408 , H01J37/3447
摘要： Embodiments of the invention generally relate to a process kit for a semiconductor processing chamber, and a semiconductor processing chamber having a kit. More specifically, embodiments described herein relate to a process kit including a cover ring, a shield, and an isolator for use in a physical deposition chamber. The components of the process kit work alone and in combination to significantly reduce particle generation and stray plasmas. In comparison with existing multiple part shields, which provide an extended RF return path contributing to RF harmonics causing stray plasma outside the process cavity, the components of the process kit reduce the RF return path thus providing improved plasma containment in the interior processing region.
摘要翻译：本发明的实施例一般涉及用于半导体处理室的处理套件和具有套件的半导体处理室。更具体地，本文所述的实施例涉及包括用于物理沉积室中的盖环，屏蔽和隔离器的处理套件。过程组件的组件单独工作并组合起来，以显着减少颗粒产生和杂散等离子体。与现有的多部分屏蔽相比，其提供了有助于RF谐波的扩展的RF返回路径，从而在处理空腔之外引起杂散等离子体，处理套件的部件降低了RF返回路径，从而在内部处理区域中提供了改进的等离子体容纳物。

7. 发明申请

WO2010114823A3 SPUTTERING TARGET FOR PVD CHAMBER 审中-公开
标题翻译： PVD室的喷射目标
公开(公告)号：WO2010114823A3
公开(公告)日：2011-01-13
申请号：PCT/US2010029171
申请日：2010-03-30
申请人： APPLIED MATERIALS INC , LIU ZHENDONG , WANG RONGJUN , TANG XIANMIN , GANDIKOTA SRINIVAS , GUNG TZA-JING , RASHEED MUHAMMAD M
发明人： LIU ZHENDONG , WANG RONGJUN , TANG XIANMIN , GANDIKOTA SRINIVAS , GUNG TZA-JING , RASHEED MUHAMMAD M
IPC分类号： H01L21/203 , C23C14/34
CPC分类号： C23C14/3407 , H01J37/342 , H01J37/3423
摘要： Target assemblies and PVD chambers including target assemblies are disclosed. The target assembly includes a target that has a concave shaped target. When used in a PVD chamber, the concave target provides more radially uniform deposition on a substrate disposed in the sputtering chamber.
摘要翻译：公开了包括目标组件的目标组件和PVD室。目标组件包括具有凹形目标的目标。当在PVD室中使用时，凹目标在设置在溅射室中的基板上提供更径向均匀的沉积。

8. 发明申请

WO2010114823A4 SPUTTERING TARGET FOR PVD CHAMBER 审中-公开
公开(公告)号：WO2010114823A4
公开(公告)日：2010-10-07
申请号：PCT/US2010/029171
申请日：2010-03-30
申请人： APPLIED MATERIALS, INC. , LIU, Zhendong , WANG, Rongjun , TANG, Xianmin , GANDIKOTA, Srinivas , GUNG, Tza-Jing , RASHEED, Muhammad M.
发明人： LIU, Zhendong , WANG, Rongjun , TANG, Xianmin , GANDIKOTA, Srinivas , GUNG, Tza-Jing , RASHEED, Muhammad M.
IPC分类号： H01L21/203 , C23C14/34
摘要： Target assemblies and PVD chambers including target assemblies are disclosed. The target assembly includes a target that has a concave shaped target. When used in a PVD chamber, the concave target provides more radially uniform deposition on a substrate disposed in the sputtering chamber.

9. 发明申请

WO2012109104A2 UNIFORMITY TUNING CAPABLE ESC GROUNDING KIT FOR RF PVD CHAMBER 审中-公开
标题翻译：用于RF PVD室的均匀调谐电容接地套件
公开(公告)号：WO2012109104A2
公开(公告)日：2012-08-16
申请号：PCT/US2012/023762
申请日：2012-02-03
申请人： APPLIED MATERIALS, INC. , RASHEED, Muhammad M. , WANG, Rongjun , NGUYEN, Thanh X. , RITCHIE, Alan A.
发明人： RASHEED, Muhammad M. , WANG, Rongjun , NGUYEN, Thanh X. , RITCHIE, Alan A.
IPC分类号： H01L21/203
CPC分类号： H01J37/34 , H01J37/32082 , H01J37/3441
摘要： Embodiments of the invention generally relate to a grounding kit for a semiconductor processing chamber, and a semiconductor processing chamber having a grounding kit. More specifically, embodiments described herein relate to a grounding kit which creates an asymmetric grounding path selected to significantly reduce the asymmetries caused by an off center RF power delivery.
摘要翻译：本发明的实施例一般涉及用于半导体处理室的接地套件和具有接地套件的半导体处理室。更具体地说，本文描述的实施例涉及一种接地套件，该接地套件产生一个非对称接地路径，该非接地套件被选择以显着地减少由偏心的RF功率输送引起的

10. 发明申请

WO2012057987A2 DEPOSITION RING AND ELECTROSTATIC CHUCK FOR PHYSICAL VAPOR DEPOSITION CHAMBER 审中-公开
标题翻译：物理气相沉积室沉积环和静电卡盘
公开(公告)号：WO2012057987A2
公开(公告)日：2012-05-03
申请号：PCT/US2011/055374
申请日：2011-10-07
申请人： APPLIED MATERIALS, INC. , RASHEED, Muhammad , MILLER, Keith A. , WANG, Rongjun
发明人： RASHEED, Muhammad , MILLER, Keith A. , WANG, Rongjun
IPC分类号： H01L21/203 , H01L21/683
CPC分类号： C23C14/50 , C23C14/3407 , C23C14/564 , C23C16/4585 , H01L21/68735
摘要： Embodiments of the invention generally relate to a process kit for a semiconductor processing chamber, and a semiconductor processing chamber having a kit. More specifically, embodiments described herein relate to a process kit including a deposition ring and a pedestal assembly. The components of the process kit work alone, and in combination, to significantly reduce their effects on the electric fields around a substrate during processing.
摘要翻译：本发明的实施例一般涉及用于半导体处理室的处理套件和具有套件的半导体处理室。更具体地说，这里描述的实施例涉及包括沉积环和基座组件的处理套件。该工艺套件的组件独自工作，并结合使用，显着降低其在加工过程中对衬底周围电场的影响。

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