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1. 发明授权

US08503814B2 Method and apparatus for spectrum estimation 失效
标题翻译：频谱估计的方法和装置
公开(公告)号：US08503814B2
公开(公告)日：2013-08-06
申请号：US12637526
申请日：2009-12-14
申请人： Oscar Ayzenberg , Vlad Fruchter
发明人： Oscar Ayzenberg , Vlad Fruchter
IPC分类号： G06K9/40
CPC分类号： G06T5/003 , G06T2207/10016 , G06T2207/20012
摘要： An apparatus and methods are provided for determining control parameters for image enhancement. In one embodiment a method for determining control parameters includes receiving image data for a first frame and calculating an adaptive threshold value based on the image data. The method includes determining a pixel slope distribution for a pixel window of the image data, wherein the pixel window is selected based on the adaptive threshold value and determining a spectrum estimation coefficient based on the pixel distribution, wherein the spectrum estimation coefficient is determined based on the spectral components of the image data. The method may then include determining one or more control parameters for enhancement of the image data based on the spectrum estimation coefficient, wherein the one or more control parameters relate to filtering parameters for adaptive enhancement of image data.
摘要翻译：提供了一种用于确定用于图像增强的控制参数的装置和方法。在一个实施例中，用于确定控制参数的方法包括接收第一帧的图像数据并基于图像数据计算自适应阈值。该方法包括确定图像数据的像素窗口的像素斜率分布，其中基于自适应阈值选择像素窗口，并且基于像素分布来确定频谱估计系数，其中基于图像数据的光谱分量。该方法然后可以包括基于频谱估计系数确定用于增强图像数据的一个或多个控制参数，其中一个或多个控制参数涉及用于图像数据的自适应增强的滤波参数。

2. 发明申请

US20150177990A1 BLOB POOLS, SELECTORS, AND COMMAND SET IMPLEMENTED WITHIN A MEMORY APPLIANCE FOR ACCESSING MEMORY 有权
标题翻译：用于访问存储器的存储器件中实现的BLOB池，选择器和命令集
公开(公告)号：US20150177990A1
公开(公告)日：2015-06-25
申请号：US14539662
申请日：2014-11-12
申请人： Keith LOWERY , Vlad FRUCHTER
发明人： Keith LOWERY , Vlad FRUCHTER
IPC分类号： G06F3/06
CPC分类号： G06F15/17331 , G06F3/0619 , G06F12/0653 , G06F12/0692 , G06F13/16 , H04L67/1097 , H04L67/2842
摘要： A memory appliance system is described and includes a plurality of memory devices storing data in a plurality of containers and a controller. The containers include metadata, relationship information associating a respective container with related containers, and a payload. The controller is configured to perform data operations on the payload of one of the containers, and based on the relationship information associating the respective container with related containers and the payload of related containers.
摘要翻译：描述了存储器具系统，并且包括在多个容器中存储数据的多个存储器件和控制器。容器包括元数据，将相应容器与相关容器相关联的关系信息和有效载荷。控制器被配置为对容器之一的有效载荷执行数据操作，并且基于将相应容器与相关容器相关联的关系信息和相关容器的有效载荷。

3. 发明授权

US5179530A Architecture for integrated concurrent vector signal processor 失效
标题翻译：集成并发矢量信号处理器架构
公开(公告)号：US5179530A
公开(公告)日：1993-01-12
申请号：US711573
申请日：1991-05-31
申请人： Alexander Genusov , Ram B. Friedlander , Peter Feldman , Vlad Fruchter , Ricardo Jaliff , Asaf Mohr , Rafi Retter
发明人： Alexander Genusov , Ram B. Friedlander , Peter Feldman , Vlad Fruchter , Ricardo Jaliff , Asaf Mohr , Rafi Retter
IPC分类号： G06F9/38 , G06F15/78 , G06F17/10
CPC分类号： G06F9/30014 , G06F15/8076 , G06F17/10 , G06F9/3004 , G06F9/30112 , G06F9/3013 , G06F9/3016 , G06F9/30167 , G06F9/30181 , G06F9/3824 , G06F9/3836 , G06F9/3838 , G06F9/3885
摘要： Multiple special purpose processing units are provided in a vector signal processor for concurrent, parallel processing, particularly of complex vectors. The principal processing units are an execution unit, a data movement unit, a control/register unit, a vector buffer unit, an instruction fetch unit, and a bus interface unit.
摘要翻译：矢量信号处理器中提供多个专用处理单元，用于并行，并行处理，特别是复杂矢量。主处理单元是执行单元，数据移动单元，控制/寄存单元，向量缓冲单元，指令获取单元和总线接口单元。

4. 发明申请

US20150177989A1 MEMORY PACKET, DATA STRUCTURE AND HIERARCHY WITHIN A MEMORY APPLIANCE FOR ACCESSING MEMORY 有权
标题翻译：内存包，数据结构和分层存储器存储器
公开(公告)号：US20150177989A1
公开(公告)日：2015-06-25
申请号：US14539628
申请日：2014-11-12
申请人： Keith LOWERY , Vlad FRUCHTER
发明人： Keith LOWERY , Vlad FRUCHTER
IPC分类号： G06F3/06
CPC分类号： G06F15/17331 , G06F3/0619 , G06F12/0653 , G06F12/0692 , G06F13/16 , H04L67/1097 , H04L67/2842
摘要： A memory appliance system is described that includes a memory unit comprising a memory unit controller and a plurality of memory devices. A reconfigurable memory structure is stored in the plurality of memory devices, wherein the memory structure comprises a plurality of variably sized containers. Each container of data includes metadata, payload, and relationship information that associates a corresponding container with one or more other containers stored in the memory structure. The controller is data structure aware such that the controller is configured to traverse the memory structure and perform operations on the memory structure based on the metadata and relationship information.
摘要翻译：描述了一种存储器装置系统，其包括包括存储器单元控制器和多个存储器件的存储器单元。可重构存储器结构存储在多个存储器件中，其中存储器结构包括多个可变尺寸的容器。每个数据容器包括将对应容器与存储在存储器结构中的一个或多个其他容器相关联的元数据，有效载荷和关系信息。控制器是数据结构感知的，使得控制器被配置为遍历存储器结构并且基于元数据和关系信息对存储器结构执行操作。

5. 发明申请

US20100183238A1 Method and Apparatus for Spectrum Estimation 失效
标题翻译：频谱估计的方法和装置
公开(公告)号：US20100183238A1
公开(公告)日：2010-07-22
申请号：US12637526
申请日：2009-12-14
申请人： Oscar Ayzenberg , Vlad Fruchter
发明人： Oscar Ayzenberg , Vlad Fruchter
IPC分类号： G06K9/40
CPC分类号： G06T5/003 , G06T2207/10016 , G06T2207/20012
摘要： An apparatus and methods are provided for determining control parameters for image enhancement. In one embodiment a method for determining control parameters includes receiving image data for a first frame and calculating an adaptive threshold value based on the image data. The method includes determining a pixel slope distribution for a pixel window of the image data, wherein the pixel window is selected based on the adaptive threshold value and determining a spectrum estimation coefficient based on the pixel distribution, wherein the spectrum estimation coefficient is determined based on the spectral components of the image data. The method may then include determining one or more control parameters for enhancement of the image data based on the spectrum estimation coefficient, wherein the one or more control parameters relate to filtering parameters for adaptive enhancement of image data.
摘要翻译：提供了一种用于确定用于图像增强的控制参数的装置和方法。在一个实施例中，用于确定控制参数的方法包括接收第一帧的图像数据并基于图像数据计算自适应阈值。该方法包括确定图像数据的像素窗口的像素斜率分布，其中基于自适应阈值选择像素窗口，并且基于像素分布来确定频谱估计系数，其中基于图像数据的光谱分量。该方法然后可以包括基于频谱估计系数确定用于增强图像数据的一个或多个控制参数，其中一个或多个控制参数涉及用于图像数据的自适应增强的滤波参数。

6. 发明授权

US5053987A Arithmetic unit in a vector signal processor using pipelined computational blocks 失效
标题翻译：使用流水线计算块的矢量信号处理器中的算术单元
公开(公告)号：US5053987A
公开(公告)日：1991-10-01
申请号：US430815
申请日：1989-11-02
申请人： Alexander Genusov , Ram B. Friedlander , Peter Feldman , Vlad Fruchter
发明人： Alexander Genusov , Ram B. Friedlander , Peter Feldman , Vlad Fruchter
IPC分类号： G06F7/48 , G06F7/50 , G06F7/52 , G06F7/57 , G06F15/78
CPC分类号： G06F7/485 , G06F15/8076 , G06F7/4806 , G06F7/483 , G06F7/4876 , G06F2207/3884
摘要： An arithmetic unit for a vector signal processor implements IEEE Standard 754 for Floating-Point Arithmetic. The arithmetic unit includes three pipelined floating-point computational blocks: a multiplier, an adder-subtracter, and an adder to provide for high computation throughput for digital signal processing (DSP) operations. The adder-subtracter and the adder have the same input operands, so that the sum and difference of these input operands can be computed simultaneously. A first and a second internal data bus are provided for transferring data and instructions within the arithmetic execution unit. The input/output operands and partial results are stored in a set of auxiliary registers. Most of these registers can be organized in pairs that for complex arithmetic computations are used to store the real and the imaginary parts of a complex operand. A register-pair can also simultaneously handle two different real operands. The operands are fetched from an internal data buffer from, for example, sources internal to the integrated circuit such as internal RAM, ROM and arithmetic registers. Computation results from the Multiplier, the Adder, and the Adder-Subtracter are temporary stored in the auxiliary registers before writing to the internal RAM or arithmetic registers of the integrated circuit. Data-flow in the vector arithmetic unit is controlled by a vector control unit.
摘要翻译：用于矢量信号处理器的算术单元实现用于浮点算术的IEEE标准754。算术单元包括三个流水线浮点计算块：乘法器，加法器 - 减法器和加法器，用于为数字信号处理（DSP）操作提供高计算吞吐量。加法器 - 减法器和加法器具有相同的输入操作数，使得可以同时计算这些输入操作数的和和差。第一和第二内部数据总线被提供用于在算术执行单元内传送数据和指令。输入/输出操作数和部分结果存储在一组辅助寄存器中。大多数这些寄存器可以成对组织，用于复杂算术计算用于存储复数操作数的实部和虚部。寄存器对也可以同时处理两个不同的实际操作数。操作数从内部数据缓冲器中取出，例如内部RAM，ROM和算术寄存器等集成电路内部的源。在写入集成电路的内部RAM或算术寄存器之前，乘法器，加法器和加法器 - 减法器的计算结果临时存储在辅助寄存器中。矢量运算单元中的数据流由矢量控制单元控制。

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