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1. 发明授权

US06269352B1 Low-voltage, very-low-power conductance mode neuron 有权
标题翻译：低电压，极低功率的电导模式神经元
公开(公告)号：US06269352B1
公开(公告)日：2001-07-31
申请号：US09461674
申请日：1999-12-14
申请人： Vito Fabbrizio , Gianluca Colli , Alan Kramer
发明人： Vito Fabbrizio , Gianluca Colli , Alan Kramer
IPC分类号： G06F1518
CPC分类号： G06N3/063 , G06N3/0635
摘要： A neural network including a number of synaptic weighting elements, and a neuron stage; each of the synaptic weighting elements having a respective synaptic input connection supplied with a respective input signal; and the neuron stage having inputs connected to the synaptic weighting elements, and being connected to an output of the neural network supplying a digital output signal. The accumulated weighted inputs are represented as conductances, and a conductance-mode neuron is used to apply nonlinearity and produce an output. The synaptic weighting elements are formed by memory cells programmable to different threshold voltage levels, so that each presents a respective programmable conductance; and the neuron stage provides for measuring conductance on the basis of the current through the memory cells, and for generating a binary output signal on the basis of the total conductance of the synaptic elements.
摘要翻译：包括许多突触加权元素和神经元阶段的神经网络; 每个突触加权元件具有被提供有相应输入信号的相应突触输入连接; 并且神经元级具有连接到突触加权元件的输入，并且连接到提供数字输出信号的神经网络的输出端。累积的加权输入被表示为电导，并且使用电导模式神经元来应用非线性并产生输出。突触加权元件由可编程为不同阈值电压电平的存储器单元形成，使得每个呈现相应的可编程电导; 并且神经元级基于通过存储器单元的电流提供测量电导，并且用于基于突触元件的总电导产生二进制输出信号。

2. 再颁专利

USRE41658E1 Low-voltage, very-low-power conductance mode neuron 有权
标题翻译：低电压，极低功率的电导模式神经元
公开(公告)号：USRE41658E1
公开(公告)日：2010-09-07
申请号：US10631323
申请日：2003-07-31
申请人： Vito Fabbrizio , Gianluca Colli , Alan Kramer
发明人： Vito Fabbrizio , Gianluca Colli , Alan Kramer
IPC分类号： G06G7/00 , G06N3/00 , G06N3/02 , G06E1/00 , G06E3/00 , G06F15/16
CPC分类号： G06N3/063 , G06N3/0635
摘要： A neural network including a number of synaptic weighting elements, and a neuron stage; each of the synaptic weighting elements having a respective synaptic input connection supplied with a respective input signal; and the neuron stage having inputs connected to the synaptic weighting elements, and being connected to an output of the neural network supplying a digital output signal. The accumulated weighted inputs are represented as conductances, and a conductance-mode neuron is used to apply nonlinearity and produce an output. The synaptic weighting elements are formed by memory cells programmable to different threshold voltage levels, so that each presents a respective programmable conductance; and the neuron stage provides for measuring conductance on the basis of the current through the memory cells, and for generating a binary output signal on the basis of the total conductance of the synaptic elements.
摘要翻译：包括许多突触加权元素和神经元阶段的神经网络; 每个突触加权元件具有被提供有相应输入信号的相应突触输入连接; 并且神经元级具有连接到突触加权元件的输入，并且连接到提供数字输出信号的神经网络的输出端。累积的加权输入被表示为电导，并且使用电导模式神经元来应用非线性并产生输出。突触加权元件由可编程为不同阈值电压电平的存储器单元形成，使得每个呈现相应的可编程电导; 并且神经元级基于通过存储器单元的电流提供测量电导，并且用于基于突触元件的总电导产生二进制输出信号。

3. 发明授权

US06212287B1 Method for identifying marking stripes of road lanes 失效
标题翻译：识别道路标志条纹的方法
公开(公告)号：US06212287B1
公开(公告)日：2001-04-03
申请号：US08951956
申请日：1997-10-17
申请人： Massimiliano Olivieri , Vito Fabbrizio , Roberto Guerrieri , Alan Kramer
发明人： Massimiliano Olivieri , Vito Fabbrizio , Roberto Guerrieri , Alan Kramer
IPC分类号： G06K900
CPC分类号： G05D1/0246 , G05D2201/0213
摘要： A method, in a system for aiding the guidance of a vehicle, for identifying marking stripes of road lanes. A road image is subjected to a convolution operation with a mask matrix so as to identify discontinuities present in the image. The resulting convolved image is compared with a threshold value and a representation of the marking stripes is determined. The mask matrix is set in such a way as to eliminate at least partially the discontinuities which do not correspond to the marking stripes.
摘要翻译：一种用于辅助车辆引导的系统中用于识别道路标线的方法。使用掩模矩阵对道路图像进行卷积运算，以识别图像中存在的不连续性。将所得到的卷积图像与阈值进行比较，并确定标记条纹的表示。掩模矩阵被设置为至少部分地消除不对应于标记条纹的不连续性。

4. 发明授权

US6041321A Electronic device for performing convolution operations 失效
标题翻译：用于执行卷积运算的电子设备
公开(公告)号：US6041321A
公开(公告)日：2000-03-21
申请号：US953956
申请日：1997-10-10
申请人： Vito Fabbrizio , Alan Kramer
发明人： Vito Fabbrizio , Alan Kramer
IPC分类号： G06F17/10 , G06N3/063 , G06F15/18
CPC分类号： G06N3/063
摘要： An electronic device for performing convolution operations comprises shift registers for receiving binary input values representative of an original matrix, synapses for storing weights correlated with a mask matrix, and neurons for outputting a binary result dependent on the sum of the binary values weighted by the synapses. Each synapse has a conductance correlated with the weight stored and dependent upon the binary input value. Each neuron generates the binary result in dependence on the total conductance of the corresponding synapses.
摘要翻译：用于执行卷积运算的电子装置包括用于接收表示原始矩阵的二进制输入值的移位寄存器，用于存储与掩模矩阵相关的权重的突触，以及用于输出取决于由突触加权的二进制值之和的二进制结果的神经元。每个突触具有与存储的权重相关的电导，并且取决于二进制输入值。每个神经元根据相应突触的总电导产生二进制结果。

5. 发明授权

US6032140A Low-voltage, very-low-power conductance mode neuron 失效
标题翻译：低电压，极低功率的电导模式神经元
公开(公告)号：US6032140A
公开(公告)日：2000-02-29
申请号：US731426
申请日：1996-10-15
申请人： Vito Fabbrizio , Gianluca Colli , Alan Kramer
发明人： Vito Fabbrizio , Gianluca Colli , Alan Kramer
IPC分类号： G06G7/60 , G06F15/18 , G06N3/06 , G06N3/063
CPC分类号： G06N3/063 , G06N3/0635
摘要： A neural network including a number of synaptic weighting elements, and a neuron stage; each of the synaptic weighting elements having a respective synaptic input connection supplied with a respective input signal; and the neuron stage having inputs connected to the synaptic weighting elements, and being connected to an output of the neural network supplying a digital output signal. The accumulated weighted inputs are represented as conductances, and a conductance-mode neuron is used to apply nonlinearity and produce an output. The synaptic weighting elements are formed by memory cells programmable to different threshold voltage levels, so that each presents a respective programmable conductance; and the neuron stage provides for measuring conductance on the basis of the current through the memory cells, and for generating a binary output signal on the basis of the total conductance of the synaptic elements.
摘要翻译：包括许多突触加权元素和神经元阶段的神经网络; 每个突触加权元件具有被提供有相应输入信号的相应突触输入连接; 并且神经元级具有连接到突触加权元件的输入，并且连接到提供数字输出信号的神经网络的输出端。累积的加权输入被表示为电导，并且使用电导模式神经元来应用非线性并产生输出。突触加权元件由可编程为不同阈值电压电平的存储器单元形成，使得每个呈现相应的可编程电导; 并且神经元级基于通过存储器单元的电流提供测量电导，并且用于基于突触元件的总电导产生二进制输出信号。

6. 发明授权

US5982608A Semiconductor variable capacitor 失效
标题翻译：半导体可变电容器
公开(公告)号：US5982608A
公开(公告)日：1999-11-09
申请号：US6269
申请日：1998-01-13
申请人： Alexander Kalnitsky , Alan Kramer , Vito Fabbrizio , Giovanni Gozzini , Bhusian Guptz , Marco Sabatini
发明人： Alexander Kalnitsky , Alan Kramer , Vito Fabbrizio , Giovanni Gozzini , Bhusian Guptz , Marco Sabatini
IPC分类号： H01G7/00 , G01B7/28 , G01L9/00 , G01P15/08 , G01P15/125 , H01L21/822 , H01L27/04 , H01G5/01 , H01G5/011 , H01G5/013
CPC分类号： G01L9/0072 , G01P15/0802 , G01P15/125 , H01G5/16
摘要： A variable capacitor in a semiconductor device is described in which the capacitance is varied by the movement of a dielectric material in the space between the plates of the capacitor in response to an external stimulus. A method of making such a variable capacitor is also described in which the capacitor is built in a layered structure with the top layer including a portion of dielectric material extending into the space between the capacitor plates. After formation of the top layer, an intermediate layer is etched away to render the top layer flexible to facilitate movement of the dielectric material in the space between the capacitor plates.
摘要翻译：描述了半导体器件中的可变电容器，其中电容根据外部刺激而在电容器的板之间的空间中的电介质材料的移动而变化。还描述了制造这种可变电容器的方法，其中电容器内置在分层结构中，顶层包括延伸到电容器板之间的空间中的介电材料的一部分。在形成顶层之后，蚀刻掉中间层以使顶层柔性以促进电介质材料在电容器板之间的空间中的移动。

7. 发明授权

US6110791A Method of making a semiconductor variable capacitor 有权
标题翻译：制造半导体可变电容器的方法
公开(公告)号：US6110791A
公开(公告)日：2000-08-29
申请号：US361348
申请日：1999-07-26
申请人： Alexander Kalnitsky , Alan Kramer , Vito Fabbrizio , Giovanni Gozzini , Bhusan Gupta , Marco Sabatini
发明人： Alexander Kalnitsky , Alan Kramer , Vito Fabbrizio , Giovanni Gozzini , Bhusan Gupta , Marco Sabatini
IPC分类号： H01G7/00 , G01B7/28 , G01L9/00 , G01P15/08 , G01P15/125 , H01L21/822 , H01L27/04 , H01L21/20
CPC分类号： G01L9/0072 , G01P15/0802 , G01P15/125 , H01G5/16
摘要： A variable capacitor in a semiconductor device is described in which the capacitance is varied by the movement of a dielectric material in the space between the plates of the capacitor in response to an external stimulus. A method of making such a variable capacitor is also described in which the capacitor is built in a layered structure with the top layer including a portion of dielectric material extending into the space between the capacitor plates. After formation of the top layer, an intermediate layer is etched away to render the top layer flexible to facilitate movement of the dielectric material in the space between the capacitor plates.
摘要翻译：描述了半导体器件中的可变电容器，其中电容根据外部刺激而在电容器的板之间的空间中的电介质材料的移动而变化。还描述了制造这种可变电容器的方法，其中电容器内置在分层结构中，顶层包括延伸到电容器板之间的空间中的介电材料的一部分。在形成顶层之后，蚀刻掉中间层以使顶层柔性以促进电介质材料在电容器板之间的空间中的移动。

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