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1. 发明授权

US5413945A Blanket N-LDD implantation for sub-micron MOS device manufacturing 失效
标题翻译：用于亚微米MOS器件制造的毯式N-LDD注入
公开(公告)号：US5413945A
公开(公告)日：1995-05-09
申请号：US289671
申请日：1994-08-12
申请人： Sun-Chieh Chien , Tzong-Shien Wu
发明人： Sun-Chieh Chien , Tzong-Shien Wu
IPC分类号： H01L21/8238 , H01L27/092 , H01L21/336
CPC分类号： H01L27/0928 , H01L21/823807
摘要： A method for making sub-micron MOS (Metal Oxide Semiconductor) devices, which do not suffer from hot carrier effect, and having improved short-channel effect and improved performance, is described. A silicon substrate with field isolation regions, P-well and N-well regions, and an oxide layer over the P-well and N-well regions is provided. The P-well region is implanted, in a substantially vertical direction, with a first conductivity-imparting dopant. Gate structures are formed over the P-well and N-well regions. A second conductivity-imparting dopant is implanted, at a large angle to the plane of the silicon substrate, that is of opposite conductivity to the first conductivity-imparting dopant, into the P-well and N-well regions, masked by the gate structures. The N-well region is implanted, in a substantially vertical direction, with a third conductivity-imparting dopant, of the same conductivity as the first conductivity-imparting dopant. Sidewall spacers are formed on the gate structures. The P-well region is implanted, in a substantially vertical direction, with a fourth conductivity-imparting dopant, of the same conductivity as the second conductivity-imparting dopant. The N-well region is implanted, in a substantially vertical direction, with a fifth conductivity-imparting dopant, of the same conductivity as the first conductivity-imparting dopant. The silicon substrate is heated to drive in the dopants.
摘要翻译：描述了一种制造不受热载流子效应的亚微米MOS（金属氧化物半导体）器件的方法，并且具有改善的短沟道效应和改进的性能。提供了具有场隔离区域的硅衬底，P阱和N阱区域以及P阱和N阱区域上的氧化物层。 P阱区域在基本上垂直的方向上用第一导电性掺杂剂注入。栅极结构形成在P阱和N阱区上。第二导电性赋予掺杂剂以与第一导电性赋予掺杂剂相反的导电性的方式与硅衬底的平面成大角度地注入由P阱和N阱区域掩蔽的栅极结构。 N阱区域在基本上垂直的方向上与具有与第一导电性赋予掺杂剂相同的导电性的第三导电性赋予掺杂剂注入。侧壁间隔件形成在栅极结构上。 P阱区域在基本上垂直的方向上与第四导电性赋予掺杂剂一样，与第二导电性赋予掺杂剂相同。在基本上垂直的方向上，用具有与赋予第一导电性的掺杂剂相同的导电性的第五导电性掺杂剂将N阱区域注入。硅衬底被加热以在掺杂剂中驱动。

2. 发明授权

US5814553A Method of fabricating self-align contact window with silicon nitride side wall 失效
标题翻译：用氮化硅侧壁制作自对准接触窗的方法
公开(公告)号：US5814553A
公开(公告)日：1998-09-29
申请号：US647410
申请日：1996-05-09
申请人： Andy Chuang , Tzong-Shien Wu
发明人： Andy Chuang , Tzong-Shien Wu
IPC分类号： H01L21/311 , H01L21/60 , H01L21/3205
CPC分类号： H01L21/76897 , H01L21/31116 , Y10S438/97
摘要： The process of the present invention has numerous advantages over the prior art. The silicon nitride side-wall spacers permit a small contact hole thus miniaturizing the cell beyond lithographic limits. The side-wall spacers composed of silicon nitride and silicon dioxide avoid to expose the polysilicon when the contact window is formed by etching step. Moreover, the highly selective etching process improve the accuracy of the contact window.
摘要翻译：本发明的方法与现有技术相比具有许多优点。氮化硅侧壁间隔物允许小的接触孔，从而使电池小于光刻极限。当通过蚀刻步骤形成接触窗口时，由氮化硅和二氧化硅组成的侧壁间隔物避免暴露多晶硅。此外，高选择性蚀刻工艺提高了接触窗的精度。

3. 发明授权

US6008080A Method of making a low power SRAM 失效
标题翻译：制造低功耗SRAM的方法
公开(公告)号：US6008080A
公开(公告)日：1999-12-28
申请号：US975488
申请日：1997-11-21
申请人： Andy Chuang , Tzong-Shien Wu , Sun-Chieh Chien
发明人： Andy Chuang , Tzong-Shien Wu , Sun-Chieh Chien
IPC分类号： H01L21/8244 , H01L27/02 , H01L27/11 , H01L21/70
CPC分类号： H01L27/11 , H01L27/0266 , H01L27/1104 , H01L27/1108
摘要： An SRAM is formed having the six transistor cell. The pull down transistors are formed so that no arsenic is implanted into the drains of the pull down transistors so that the drains of the pull down transistors are doped only by phosphorus implantation. The sources of the pull down transistors are doped with an LDD configuration of phosphorus ions and then a further implantation of arsenic ions is performed. This can conveniently be accomplished by providing an opening in the mask used to implant impurities into the source/drain regions of the ESD protection circuit.
摘要翻译：形成具有六个晶体管单元的SRAM。形成下拉晶体管，使得没有砷被注入到下拉晶体管的漏极中，使得下拉晶体管的漏极仅通过磷注入掺杂。下拉晶体管的源极掺杂有磷离子的LDD配置，然后进一步注入砷离子。这可以通过在用于将杂质注入到ESD保护电路的源极/漏极区域中的掩模中提供开口来方便地实现。

4. 发明授权

US5506438A Semiconductor device with two different threshold voltages 失效
标题翻译：具有两个不同阈值电压的半导体器件
公开(公告)号：US5506438A
公开(公告)日：1996-04-09
申请号：US387434
申请日：1995-02-13
申请人： Chen-Chiu Hsue , Sun-Chieh Chien , Lee C. Yuan , Tzong-Shien Wu
发明人： Chen-Chiu Hsue , Sun-Chieh Chien , Lee C. Yuan , Tzong-Shien Wu
IPC分类号： H01L21/8238 , H01L29/76 , H01L29/94
CPC分类号： H01L21/823807
摘要： A semiconductor MOSFET device manufactured by a process starting with a doped semiconductor substrate with a P-well and an N-well and field oxide structures on the surface of the P-well and the N-well separating the surfaces of the P-well and the N-well into separate regions and a silicon dioxide film on the remainder of the surface of the P-well and the N-well comprising the steps as follows: forming a mask over the N-well and an under sized mask over one of the separate regions of the P-well performing a field ion implantation of V.sub.t ' ions into the P-well, removing the mask over the portion of the P-well, performing a blanket ion implantation of V.sub.t1 ions over the entire device.
摘要翻译：一种半导体MOSFET器件，其通过以P阱和N阱的掺杂半导体衬底开始的工艺和在P阱的表面上的N阱和N阱分离P阱的表面，以及将N阱分成不同的区域，并在P阱和N阱的表面的其余部分上形成二氧化硅膜，其包括以下步骤：在N阱上形成掩模，并在下面的掩模上形成掩模 P阱的单独区域执行Vt离子的离子注入到P阱中，在P阱的部分上去除掩模，在整个器件上执行Vt1离子的覆盖离子注入。

5. 发明授权

US5416038A Method for producing semiconductor device with two different threshold voltages 失效
标题翻译：具有两个不同阈值电压的半导体器件的制造方法
公开(公告)号：US5416038A
公开(公告)日：1995-05-16
申请号：US249307
申请日：1994-05-25
申请人： Chen-Chiu Hsue , Sun-Chieh Chien , Lee C. Yuan , Tzong-Shien Wu
发明人： Chen-Chiu Hsue , Sun-Chieh Chien , Lee C. Yuan , Tzong-Shien Wu
IPC分类号： H01L21/8238 , H01L21/70
CPC分类号： H01L21/823807
摘要： A semiconductor MOSFET device manufactured by a process starting with a doped semiconductor substrate with a P-well and an N-well and field oxide structures on the surface of the P-well and the N-well separating the surfaces of the P-well and the N-well into separate regions and a silicon dioxide film on the remainder of the surface of the P-well and the N-well comprising the steps as follows: forming a mask over the N-well and an under sized mask over one of the separate regions of the P-well performing a field ion implantation of V.sub.t ' ions into the P-well, removing the mask over the portion of the P-well, performing a blanket ion implantation of V.sub.t1 ions over the entire device.
摘要翻译：一种半导体MOSFET器件，其通过以P阱和N阱的掺杂半导体衬底开始的工艺和在P阱的表面上的N阱和N阱分离P阱的表面，以及将N阱分成不同的区域，并在P阱和N阱的表面的其余部分上形成二氧化硅膜，其包括以下步骤：在N阱上形成掩模，并在下面的掩模上形成掩模 P阱的单独区域执行Vt离子的离子注入到P阱中，在P阱的部分上去除掩模，在整个器件上执行Vt1离子的覆盖离子注入。

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