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1. 发明申请

US20110132644A1 METAL BASE CIRCUIT BOARD 有权
标题翻译：金属基座电路板
公开(公告)号：US20110132644A1
公开(公告)日：2011-06-09
申请号：US12994507
申请日：2009-05-21
申请人： Taiki Nishi , Takeshi Miyakawa , Kiyokazu Yamazaki , Takashi Saiki
发明人： Taiki Nishi , Takeshi Miyakawa , Kiyokazu Yamazaki , Takashi Saiki
IPC分类号： H05K1/03
CPC分类号： H05K1/056 , F21K9/00 , H01L25/0753 , H01L33/46 , H01L33/60 , H01L2924/0002 , H05K1/0271 , H05K1/0274 , H05K3/0061 , H05K3/285 , H05K2201/0209 , H05K2201/068 , H05K2201/09781 , H05K2201/10106 , H05K2201/2054 , Y10T29/49117 , Y10T29/49126 , Y10T29/49165 , Y10T428/12569 , Y10T428/24917 , Y10T428/24926 , Y10T428/252 , H01L2924/00
摘要： Lifespan of LEDs can be lengthened, and the workability of the printed circuit board during circuit formation and during LED mounting can be improved.A metal base circuit board, having an insulating layer with a linear expansion coefficient of 60 ppm per degree C. or higher and 120 ppm per degree C. or lower, a metal foil provided on one side of the insulating layer, comprising a metal material with a linear expansion coefficient of 10 ppm per degree C. or higher and 35 ppm per degree C. or lower, a circuit portion and a non-circuit potion having a linear expansion coefficient of 10 ppm per degree C. or higher and 35 ppm per degree C. or lower, and a white film formed on top of the insulating layer, circuit portion, and non-circuit portion, the total sum of the areas of the non-circuit portion and the circuit portion on top of the insulating layer being 50% or higher and 95% or lower relative to the area of the metal foil, and the relation between the linear expansion coefficients of each of the materials being: linear expansion coefficient of insulating layer>linear expansion coefficient of metal foil>linear expansion coefficient of circuit portion and non-circuit portion.
摘要翻译： LED的寿命可以延长，并且可以提高电路形成期间和LED安装期间印刷电路板的可加工性。一种金属基底电路板，具有线性膨胀系数为60ppm /℃以上且120ppm /℃以下的绝缘层，设置在绝缘层一侧的金属箔，其包含金属材料线性膨胀系数为10ppm /℃以上，35ppm /℃以下，具有线性膨胀系数为10ppm /℃以上且35ppm的电路部分和非电路部分以及形成在绝缘层，电路部分和非电路部分之上的白色膜，绝缘层顶部的非电路部分和电路部分的面积的总和相对于金属箔的面积为50％以上且95％以下，各材料的线膨胀系数之间的关系为：绝缘层的线膨胀系数>金属箔的线膨胀系数>线膨胀系数o f电路部分和非电路部分。

2. 发明申请

US20100255668A1 Field effect transistors with different gate widths 有权
公开(公告)号：US20100255668A1
公开(公告)日：2010-10-07
申请号：US12817508
申请日：2010-06-17
申请人： Hiroshi NOMURA , Takashi Saiki , Tsunehisa Sakoda
发明人： Hiroshi NOMURA , Takashi Saiki , Tsunehisa Sakoda
IPC分类号： H01L21/8234
CPC分类号： H01L21/823842 , H01L21/82385
摘要： Four regions (a narrow NMOS region, a wide NMOS region, a wide PMOS region, and a narrow PMOS region) are defined on a semiconductor substrate. Then, after a gate insulating film and a polysilicon film are sequentially formed on the semiconductor substrate, n-type impurities are introduced into the polysilicon film in the wide NMOS region. Next, by patterning the polysilicon film, gate electrodes are formed in the four regions. Then, n-type impurities are introduced into the gate electrodes in the narrow NMOS region and the wide NMOS region. As a result, an impurity concentration of the gate electrode in the narrow NMOS region becomes lower than that of the gate electrode in the wide NMOS region.

3. 发明申请

US20100019919A1 DOOR ASSEMBLY INCLUDING A TOUCH SENSITIVE PORTION FOR CONTROLLING AUTOMATED DOOR MOVEMENT 有权
标题翻译：门组件包括用于控制自动门运动的触感敏感部分
公开(公告)号：US20100019919A1
公开(公告)日：2010-01-28
申请号：US12092155
申请日：2006-09-12
申请人： Pei-Yuan Peng , Jaime A. Rivera , Atsushi Yamada , Takashi Saiki
发明人： Pei-Yuan Peng , Jaime A. Rivera , Atsushi Yamada , Takashi Saiki
IPC分类号： G08B21/00
CPC分类号： B66B13/26
摘要： An assembly (20) for controlling movement of an automatically moveable door panel (22) includes a sensor (30, 32, 34) positioned on at least one of a door panel (22) or a door frame member (24, 26). The sensitive portion provides an indication of when an object is in contact with or in very close proximity to a sensitive portion. A sensitive portion is established over an area of the door or door frame member at which an object may become caught during automated door movement. A disclosed example includes using an electromechanical film as a sensor so that the sensitive portion is responsive to pressure applied by the object on the sensitive portion. Another disclosed example includes a field effect sensor that generates an electric field that is at least partially interrupted when an object contacts or comes in very close proximity to the sensitive portion. Automated movement of a door is controlled responsive to an indication of the presence of an object in a location where the object may become caught during automatic movement of the door.
摘要翻译：用于控制可自动移动的门板（22）的运动的组件（20）包括定位在门板（22）或门框架构件（24,26）中的至少一个上的传感器（30,32,34）。敏感部分提供对象何时与敏感部分接触或非常接近敏感部分的指示。在门或门框构件的区域内建立敏感部分，在自动门移动期间物体可能被卡住。所公开的示例包括使用机电膜作为传感器，使得敏感部分响应于物体在敏感部分上施加的压力。另一个公开的示例包括场效应传感器，其产生当物体接触或非常接近敏感部分时至少部分中断的电场。响应于在门的自动移动期间物体可能被卡住的位置处的物体的存在的指示来控制门的自动运动。

4. 发明申请

US20070128772A1 Metal-base circuit board and its manufacturing method 有权
标题翻译：金属基电路板及其制造方法
公开(公告)号：US20070128772A1
公开(公告)日：2007-06-07
申请号：US10553076
申请日：2004-04-15
申请人： Naomi Yonemura , Katunori Yashima , Yoshihiko Tsujimura , Hidenori Ishikura , Takashi Saiki
发明人： Naomi Yonemura , Katunori Yashima , Yoshihiko Tsujimura , Hidenori Ishikura , Takashi Saiki
IPC分类号： H01L21/82 , H01L23/02
CPC分类号： H01L23/66 , H01L21/4857 , H01L23/142 , H01L23/3735 , H01L23/3736 , H01L23/49822 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/16 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/0566 , H01L2224/05666 , H01L2224/45111 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45155 , H01L2224/4516 , H01L2224/45166 , H01L2224/48091 , H01L2224/48227 , H01L2224/48237 , H01L2224/48472 , H01L2224/48611 , H01L2224/48624 , H01L2224/48639 , H01L2224/48644 , H01L2224/48647 , H01L2224/48655 , H01L2224/48666 , H01L2224/48711 , H01L2224/48724 , H01L2224/48739 , H01L2224/48747 , H01L2224/48755 , H01L2224/48766 , H01L2224/48839 , H01L2224/48844 , H01L2224/48847 , H01L2224/48855 , H01L2224/4886 , H01L2224/48866 , H01L2224/4911 , H01L2224/85411 , H01L2224/85424 , H01L2224/85439 , H01L2224/85455 , H01L2224/8546 , H01L2224/85466 , H01L2924/00011 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01039 , H01L2924/01045 , H01L2924/01047 , H01L2924/0105 , H01L2924/01056 , H01L2924/01061 , H01L2924/01063 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/13091 , H01L2924/14 , H01L2924/19043 , H01L2924/19051 , H01L2924/30105 , H05K1/0224 , H05K1/024 , H05K1/025 , H05K3/0061 , H05K2201/0187 , H05K2201/0209 , H05K2201/09745 , H01L2924/00014 , H01L2924/00 , H01L2224/48811 , H01L2224/48824 , H01L2224/48744 , H01L2224/4876 , H01L2224/4866
摘要： A metal base circuit board to be used for a hybrid integrated circuit, including circuits provided on a metal plate via an insulating layer, a power semiconductor mounted on the circuit, and a control semiconductor to control the power semiconductor, provided on the circuit. A low capacitance portion is embedded under a circuit portion on which the control semiconductor is mounted, preferably. The low capacitance portion is made of a resin containing an inorganic filler and has a dielectric constant of from 2 to 9.
摘要翻译：用于混合集成电路的金属基底电路板，包括经由绝缘层设置在金属板上的电路，安装在电路上的功率半导体以及控制半导体以控制电路上的功率半导体。优选地，将低电容部分嵌入在其上安装有控制半导体的电路部分的下方。低电容部由含有无机填料的树脂构成，介电常数为2〜9。

5. 发明申请

US20060252200A1 Semiconductor device and method of manufacturing thereof 有权
公开(公告)号：US20060252200A1
公开(公告)日：2006-11-09
申请号：US11486294
申请日：2006-07-14
申请人： Takashi Saiki
发明人： Takashi Saiki
IPC分类号： H01L21/8242
CPC分类号： H01L29/6659 , H01L21/2652 , H01L21/28247 , H01L21/823814 , H01L21/823828 , H01L21/823857 , H01L21/823864 , H01L29/6656
摘要： A silicon nitride film having a thickness of 3 nm or less is formed on the surfaces of a P-well and N-well, as well as on the upper and side surfaces of a gate electrode, in which the silicon nitride film can be formed, for example, by exposing the surface of the P-well and N-well, and the upper and side surfaces of the gate electrode to a nitrogen-gas-containing plasma using a magnetron RIE apparatus. Then, pocket layers, extension layers and source/drain layers are formed while leaving the silicon nitride film unremoved.

6. 发明申请

US20060079087A1 Method of producing semiconductor device 审中-公开
标题翻译：半导体器件的制造方法
公开(公告)号：US20060079087A1
公开(公告)日：2006-04-13
申请号：US11041217
申请日：2005-01-25
申请人： Kazuo Kawamura , Satoshi Inagaki , Takashi Saiki , Ryou Nakamura
发明人： Kazuo Kawamura , Satoshi Inagaki , Takashi Saiki , Ryou Nakamura
IPC分类号： H01L21/44 , H01L21/4763 , H01L21/336
CPC分类号： H01L21/02186 , H01L21/26513 , H01L21/28052 , H01L21/28518 , H01L21/318 , H01L29/4933 , H01L29/665
摘要： A method of producing a semiconductor device is disclosed that is able to reduce fluctuations of a sheet resistance of a silicide layer in the semiconductor device formed by a salicide process. When depositing a titanium nitride film on a cobalt film in the salicide process, the thickness of the titanium nitride film is set to be sufficiently small so that a nano-grain structure or an amorphous structure is formed in the titanium nitride film. In the titanium nitride film, the titanium composition is enriched.
摘要翻译：公开了一种制造半导体器件的方法，其能够减少通过自对准硅化物工艺形成的半导体器件中的硅化物层的薄层电阻的波动。当在自对准硅化物工艺中在钴膜上沉积氮化钛膜时，将氮化钛膜的厚度设定得足够小，使得在氮化钛膜中形成纳米晶粒结构或非晶结构。在氮化钛膜中，钛组合物富集。

7. 发明授权

US07633124B2 Semiconductor device and method of manufacturing thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07633124B2
公开(公告)日：2009-12-15
申请号：US11486112
申请日：2006-07-14
申请人： Takashi Saiki
发明人： Takashi Saiki
IPC分类号： H01L29/94 , H01L29/76
CPC分类号： H01L29/6659 , H01L21/2652 , H01L21/28247 , H01L21/823814 , H01L21/823828 , H01L21/823857 , H01L21/823864 , H01L29/6656
摘要： A silicon nitride film having a thickness of 3 nm or less is formed on the surfaces of a P-well and N-well, as well as on the upper and side surfaces of a gate electrode, in which the silicon nitride film can be formed, for example, by exposing the surface of the P-well and N-well, and the upper and side surfaces of the gate electrode to a nitrogen-gas-containing plasma using a magnetron RIE apparatus. Then, pocket layers, extension layers and source/drain layers are formed while leaving the silicon nitride film unremoved.
摘要翻译：在P阱和N阱的表面上以及可以形成氮化硅膜的栅电极的上表面和侧表面上形成厚度为3nm以下的氮化硅膜例如通过使用磁控管RIE装置将P阱和N阱的表面以及栅电极的上侧面和侧面暴露于含氮气体的等离子体。然后，在不留下氮化硅膜的同时形成袋层，延伸层和源极/漏极层。

8. 发明申请

US20080283924A1 Semiconductor device and method for fabricating the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20080283924A1
公开(公告)日：2008-11-20
申请号：US11987156
申请日：2007-11-28
申请人： Takashi Saiki , Katsuaki Okoshi , Yuka Hayami
发明人： Takashi Saiki , Katsuaki Okoshi , Yuka Hayami
IPC分类号： H01L29/78
CPC分类号： H01L21/768 , H01L23/3171 , H01L2924/0002 , H01L2924/3511 , H01L2924/00
摘要： The semiconductor device comprises a silicon wafer 10, a multilayer interconnection 12 buried in inter-layer insulation film formed on the upper surface of the silicon wafer 10, and a silicon nitride film 16b which is formed on the back surface of the silicon wafer 10 and is an insulation film having a tensile stress, relaxing a stress exerted to the silicon wafer 10 by the inter-layer insulation films in which the multilayer interconnection 12 is buried.
摘要翻译：半导体器件包括硅晶片10，埋在形成在硅晶片10的上表面上的层间绝缘膜中的多层布线12和形成在硅晶片10的背面上的氮化硅膜16b 并且是具有拉伸应力的绝缘膜，通过其中埋设多层互连12的层间绝缘膜来缓和施加到硅晶片10的应力。

9. 发明授权

US07319066B2 Semiconductor device and method for fabricating the same 有权
公开(公告)号：US07319066B2
公开(公告)日：2008-01-15
申请号：US10973391
申请日：2004-10-27
申请人： Takashi Saiki , Katsuaki Okoshi , Yuka Hayami
发明人： Takashi Saiki , Katsuaki Okoshi , Yuka Hayami
IPC分类号： H01L29/72
CPC分类号： H01L21/768 , H01L23/3171 , H01L2924/0002 , H01L2924/3511 , H01L2924/00
摘要： The semiconductor device comprises a silicon wafer 10, a multilayer interconnection 12 buried in inter-layer insulation film formed on the upper surface of the silicon wafer 10, and a silicon nitride film 16b which is formed on the back surface of the silicon wafer 10 and is an insulation film having a tensile stress, relaxing a stress exerted to the silicon wafer 10 by the inter-layer insulation films in which the multilayer interconnection 12 is buried.

10. 发明授权

US07221009B2 Semiconductor device 有权
公开(公告)号：US07221009B2
公开(公告)日：2007-05-22
申请号：US10273993
申请日：2002-10-21
申请人： Takashi Saiki
发明人： Takashi Saiki
IPC分类号： H01L31/112
CPC分类号： H01L29/6659 , H01L21/823814 , H01L21/823835 , H01L29/6656 , H01L29/7833
摘要： A dose of arsenic for an extension region in an NMOS transistor is in a range from 5×1014 to 2×1015 ions/cm2 and preferably in a range from 1.1×1015 to 1.5×1015 ions/cm2. Also, in addition to arsenic, a low concentration of phosphorus is doped into the extension region by ion implantation. Consequently, with a semiconductor device of the CMOS structure, it is possible to prevent unwanted creeping of silicide that occurs often in the shallow junction region depending on a concentration of an impurity having a low diffusion coefficient as represented by arsenic. Further, not only can the resistance in the shallow junction region be lowered, but also an amount of overlaps can be optimized in each transistor.

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