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1. 发明专利

CA2005014A1 SYSTEM FOR CROSS-CONNECTING HIGH SPEED DIGITAL SONET SIGNALS 未知
公开(公告)号：CA2005014A1
公开(公告)日：1990-06-09
申请号：CA2005014
申请日：1989-12-08
申请人： TRANSWITCH CORPORATION
发明人： UPP, DANIEL C. , COCHRAN, WILLIAM T.
IPC分类号： H04B10/27 , H04L12/66 , H04Q3/52 , H04Q11/04

2. 发明申请

US20040062129A1 Method and apparatus for enhancing the efficiency of dynamic RAM 审中-公开
标题翻译：提高动态RAM效率的方法和装置
公开(公告)号：US20040062129A1
公开(公告)日：2004-04-01
申请号：US10259013
申请日：2002-09-27
申请人： TranSwitch Corporation
发明人： Ronald P. Novick , Andrew J. Eckhardt
IPC分类号： G11C005/00
CPC分类号： G11C11/4096 , G11C7/1018 , G11C7/1072 , G11C11/4087
摘要： Methods for enhancing the efficiency of SDRAM include dividing all of the data blocks into at least two parts and storing each part in a different bank of memory. Specifically, the first part of each data block is stored in the first bank of memory and subsequent parts are stored in other banks. Since every data block begins in one bank and ends in another bank, no memory bank is ever accessed twice consecutively. In this manner it is always possible to perform precharge and row activation for the next data access while finishing the present data access. The methods of the invention are illustrated in conjunction with the storage and retrieval of ATM cells.
摘要翻译：提高SDRAM效率的方法包括将所有数据块分成至少两部分，并将每个部分存储在不同的存储体中。具体地说，每个数据块的第一部分被存储在第一存储器组中，并且随后的部分被存储在其他存储体中。由于每个数据块都在一个银行开始，而在另一个银行结束，所以不会连续两次访问存储器。以这种方式，在完成当前数据访问的同时，总是可以对下一次数据访问执行预充电和行激活。结合ATM信元的存储和检索来说明本发明的方法。

3. 发明申请

US20020154659A1 Methods and apparatus for retiming and realigning sonet signals 失效
标题翻译：重新定位和重新调整sonet信号的方法和装置
公开(公告)号：US20020154659A1
公开(公告)日：2002-10-24
申请号：US09768430
申请日：2001-01-24
申请人： TranSwitch Corporation
发明人： Kumar Shakti Singh , Pawan Goyal , Arnab Basak , Vikas Kumar , Daniel C. Upp
IPC分类号： H04J003/04
CPC分类号： H04J3/076 , H04J3/0623
摘要： Methods for retiming and realigning SONET signals include demultiplexing STS-1 signals from an STS-3 signal, buffering each of the three signals in a FIFO, determining the FIFO depth over time, determining a pointer leak rate based in part on FIFO depth and also based on the rate of received pointer movements. For a 28-byte deep FIFO, if the depth of a FIFO is 12-16 bytes, no pointer leaking is performed. If the depth is 0-4 bytes, an immediate positive leak is performed. If the depth is 24-28, an immediate negative leak is performed. If the depth is 5-11 bytes a calculated positive leak is performed. If the depth is 17-23 bytes, a calculated negative leak is performed. The calculated leak rates are based on the net number of pointer movements (magnitude of positive and negative movements summed) received every 32 seconds (256,000 frames).
摘要翻译：重新定时和重新对准SONET信号的方法包括从STS-3信号解复用STS-1信号，缓冲FIFO中的三个信号中的每一个，确定FIFO深度随时间的推移，部分地基于FIFO深度确定指针泄漏率基于接收到的指针移动速率。对于28字节深FIFO，如果FIFO的深度为12-16字节，则不会执行指针泄漏。如果深度为0-4字节，则会立即进行正面泄漏。如果深度为24-28，则立即产生负泄漏。如果深度为5-11字节，则执行计算的正泄漏。如果深度为17-23字节，则执行计算的负泄漏。计算的泄漏率基于每32秒（256,000帧）接收的指针移动的净数（正和负移动相加的大小）。

4. 发明申请

US20130217274A1 CONNECTOR FOR ACHIEVING COMPLETE INTEROPERABILITY BETWEEN DIFFERENT TYPES OF DATA AND MULTIMEDIA INTERFACES 审中-公开
标题翻译：在不同类型的数据和多媒体接口之间实现完全互补的连接器
公开(公告)号：US20130217274A1
公开(公告)日：2013-08-22
申请号：US13852559
申请日：2013-03-28
申请人： Transwitch Corporation
发明人： Amir Bar-Niv , Ziv Kabiry , Shlomy Chaikin
IPC分类号： H01R27/00
CPC分类号： H01R27/00 , G09G5/006 , H01R27/02 , H01R29/00
摘要： A universal connector for enabling interoperability between different types of data interfaces and multimedia interfaces comprises a housing; and a plurality of contact pins arranged in the housing, wherein the plurality of contact pins provide connectivity for multimedia display interface signals and data interface signals, wherein the housing includes a first part and a second part coupled together, wherein the first part includes a first group of contact pins and the second part includes a second group of contact pins, wherein the first group of contact pins provides connectivity to a data interface and the second group of contact pins provides, in part, connectivity to a multimedia interface.
摘要翻译：用于实现不同类型的数据接口和多媒体接口之间的互操作性的通用连接器包括壳体; 以及布置在所述壳体中的多个接触针，其中所述多个接触针提供用于多媒体显示接口信号和数据接口信号的连接性，其中所述壳体包括联接在一起的第一部分和第二部分，其中所述第一部分包括第一部分一组接触引脚和第二部分包括第二组接触引脚，其中第一组接触引脚提供与数据接口的连接性，并且第二组接触引脚部分地提供与多媒体接口的连接性。

5. 发明申请

US20030147416A1 Extendible asynchronous and synchronous interface bus for broadband access 失效
标题翻译：可扩展的异步和同步接口总线，用于宽带接入
公开(公告)号：US20030147416A1
公开(公告)日：2003-08-07
申请号：US10072329
申请日：2002-02-06
申请人： TranSwitch Corporation
发明人： John F. Gilsdorf , Yung-Yuan Yang
IPC分类号： H04L012/403
CPC分类号： H04L12/6418 , H04L2012/6435
摘要： Apparatus for simultaneously transferring synchronous and asynchronous signals among broadband access devices includes a data bus, a clock bus, and a plurality of control lines which are used to indicate the type of data being carried on the bus. According to the methods of the invention, data is transferred on the bus in a repeating frame having a plurality of slots, each slot being defined as one bus clock cycle. Each slot may contain a synchronous or asynchronous data signal and one or more of the control lines are asserted during the slot time of the data to indicate the type of data. Two embodiments are provided. One utilizes a 25 MHz clock bus and a repeating frame of three hundred thirty-six slots. The other utilizes a 75 MHz clock bus and a repeating frame of one thousand eight slots.
摘要翻译：用于在宽带接入设备之间同时传送同步和异步信号的设备包括数据总线，时钟总线以及用于指示在总线上承载的数据类型的多个控制线。根据本发明的方法，数据在具有多个时隙的重复帧中在总线上传送，每个时隙被定义为一个总线时钟周期。每个时隙可以包含同步或异步数据信号，并且在数据的时隙时间期间断言一个或多个控制线以指示数据的类型。提供了两个实施例。一个使用25MHz时钟总线和三百三十六个时隙的重复帧。另一个使用75MHz时钟总线和一千八个时隙的重复帧。

6. 发明申请

US20030099193A1 Multiport non-blocking high capacity ATM and packet switch 有权
标题翻译：多端口非阻塞高容量ATM和分组交换机
公开(公告)号：US20030099193A1
公开(公告)日：2003-05-29
申请号：US10000272
申请日：2001-11-02
申请人： TranSwitch Corporation
发明人： Zheng Liu , Jiu An , Terry Xian , Ronald P. Novick
IPC分类号： H04J001/16 , H04J003/14
CPC分类号： G01N33/586
摘要： A multiport non-blocking high capacity ATM and packet switch is a single chip switching solution for ATM and packet systems. It is capable of 8null8 switching of 800 Mbit/s per port in both directions. The ports support UTOPIA Level 2 interfaces. The switch is non-blocking and lossless, incorporating a backpressure mechanism for eliminating congestion toward any one port. The switch supports prioritized and variable size cell and packet switching.
摘要翻译：多端口非阻塞高容量ATM和分组交换机是用于ATM和分组系统的单芯片交换解决方案。它能够在双向方向上每端口800兆比特的8×8切换。端口支持UTOPIA 2级接口。该开关是非阻塞和无损的，结合了一个背压机制，用于消除任何一个端口的拥塞。交换机支持优先级和可变大小小区和分组交换。

7. 发明申请

US20140105230A1 CONNECTOR AND INTERFACE CIRCUIT FOR SIMULTANEOUS CONTENT STREAMING AND USER DATA FROM HANDHELD DEVICES 有权
标题翻译：用于同步内容流的连接器和接口电路以及手持设备的用户数据
公开(公告)号：US20140105230A1
公开(公告)日：2014-04-17
申请号：US13652757
申请日：2012-10-16
申请人： TRANSWITCH CORPORATION
发明人： Ziv Kabiry , Amir Bar-Niv , Shlomy Chaikin
IPC分类号： H04J3/02
CPC分类号： H04J3/02 , H02J7/00 , H02J7/0027 , H02J2007/0096
摘要： An apparatus for enabling simultaneous multimedia content and user data streaming from a handheld device to a display device is disclosed. The apparatus enables power charging of the handheld device while streaming the multimedia content and the user data from the handheld device. The apparatus comprises a data-multimedia-power interface (DMPI) connector installed in the handheld device and designed to enable the transport of at least high definition multimedia signals, data signals, a power signal, and control signals between the handheld device and the display device; and a DMPI circuit for multiplexing the high definition multimedia signals with the data signals, to enable simultaneous streaming of the respective multimedia content and the user data to the display device, wherein the DMPI circuit further extracts a power signal from the display device for power charging of the display device.
摘要翻译：公开了一种用于实现从手持设备到显示设备的同时多媒体内容和用户数据流传输的设备。该装置使得能够从手持设备流式传输多媒体内容和用户数据时手持设备的电力充电。该装置包括安装在手持设备中的数据 - 多媒体 - 电源接口（DMPI）连接器，并被设计成能够在手持设备和显示器之间传输至少高分辨率多媒体信号，数据信号，功率信号和控制信号设备; 以及用于将高分辨率多媒体信号与数据信号多路复用的DMPI电路，以使得能够将各个多媒体内容和用户数据同时流传输到显示设备，其中DMPI电路还从显示设备中提取电源信号以进行充电的显示装置。

8. 发明申请

US20040258072A1 Method and apparatus for fair queueing of data packets 失效
标题翻译：用于公平排队数据包的方法和装置
公开(公告)号：US20040258072A1
公开(公告)日：2004-12-23
申请号：US10601517
申请日：2003-06-23
申请人： TranSwitch Corporation
发明人： Koen Deforche
IPC分类号： H04L012/56
CPC分类号： H04L47/56 , H04L47/50 , H04L47/527
摘要： A packet scheduling method and apparatus is described for enqueuing incoming data packets in sessions, and for storing the sessions in sequential order in service-groups. Each service-group is assigned a nominal service-interval in which time a data packet is to be transmitted, the nominal service-interval of one service-group being faster than the nominal service-interval of another service-group. Within one service-group, one session is serviced until the nominal service-interval of any of the service-groups where there is at least one data packet to be sent is exceeded.
摘要翻译：描述了一种分组调度方法和装置，用于对进入的会话中的数据分组进行排队，并用于按照服务组中的顺序存储会话。每个服务组被分配一个标称服务间隔，在该时间间隔内传输一个数据包，一个服务组的标称服务间隔比另一个服务组的标称服务间隔更快。在一个服务组内，一个会话被服务，直到超过要发送至少一个数据包的任何服务组的标称服务间隔。

9. 发明申请

US20030169773A1 Desynchronizer having ram based shared digital phase locked loops and sonet high density demapper incorporating same 失效
标题翻译： Desynchronizer具有基于ram的共享数字锁相环和sonet高密度解映射器
公开(公告)号：US20030169773A1
公开(公告)日：2003-09-11
申请号：US10094768
申请日：2002-03-11
申请人： TranSwitch Corporation
发明人： John F. Gilsdorf
IPC分类号： H04J003/06
CPC分类号： H04J3/076 , H03L7/07
摘要： A SONET demapper includes three desynchronizers, each of which includes a RAM-based, shared digital phase locked loop, shared elastic storage, and twenty-eight divide-by 33/34/44/45 counters. Unlike a conventional desynchronizer which uses separate FIFOs for each of the twenty-eight T1/E1 channels, the elastic storage for each channel is an addressed portion of a shared block of RAM. Each desynchronizer generates a clock for each of the twenty-eight T1/E1 channels based on a FIFO depth count for each channel which is derived from a read pointer, an nulleffective write pointernull, and the divide-by clock for the channel. Each desynchronizer can desynchronize both T1 and E1 signals as well as a combination of these signals. In addition, the invention combines the leak FIFO and desynchronizer FIFO into a single FIFO with an effective write pointer. This eliminates the need to maintain separate counters and pointers for separate FIFOs.
摘要翻译： SONET解映射器包括三个去同步器，每个去同步器包括一个基于RAM的共享数字锁相环，共享弹性存储器以及二十八个除法器33/34/44/45计数器。与对于二十八个T1 / E1通道中的每一个使用单独的FIFO的常规去同步器不同，每个通道的弹性存储器是RAM的共享块的寻址部分。每个去同步器基于从读指针，“有效写指针”和通道的分频时钟导出的每个通道的FIFO深度计数，为28个T1 / E1通道中的每一个生成时钟。每个去同步器可以同步T1和E1信号以及这些信号的组合。此外，本发明将泄漏FIFO和去同步器FIFO组合成具有有效写指针的单个FIFO。这样就不需要为单独的FIFO维护单独的计数器和指针。

10. 发明授权

US08878590B2 Techniques for switching between AC-coupled connectivity and DC-coupled connectivity 有权
标题翻译：用于在交流耦合连接和直流耦合连接之间切换的技术
公开(公告)号：US08878590B2
公开(公告)日：2014-11-04
申请号：US13745011
申请日：2013-01-18
申请人： TranSwitch Corporation
发明人： Yaron Slezak
IPC分类号： H03L5/00
CPC分类号： H03K19/017509
摘要： A circuit for switching between an AC-coupled connectivity and DC-coupled connectivity of a multimedia interface. The circuit comprises a current source connected in series to a wire of the multimedia interface and a coupling capacitor; and a termination resistor connected to the current source and to the coupling capacitor, wherein the circuit is connected in series between a source line driver and a sink line receiver of the multimedia interface, wherein the source line driver supports both the AC-coupled connectivity and the DC-coupled connectivity and the sink line receiver supports any one of the AC-coupled connectivity and the DC-coupled connectivity, wherein the current source and the termination resistor allows the setting of voltage levels of signals received at the sink line receiver to voltage levels defined by the multimedia interface thereby to switch to the coupling connectivity type required by the multimedia interface at which the sink line receiver operates.
摘要翻译：用于在AC耦合连接和多媒体接口的DC耦合连接之间切换的电路。电路包括与多媒体接口的线串联连接的电流源和耦合电容器; 以及连接到电流源和耦合电容器的终端电阻器，其中电路串联连接在多媒体接口的源极线驱动器和吸收线接收器之间，其中源极线驱动器支持AC耦合连接和 DC耦合连接和吸收线接收器支持AC耦合连接和DC耦合连接中的任何一个，其中电流源和终端电阻器允许将在吸收线接收器处接收的信号的电压电平设置为电压由多媒体接口定义的级别，从而切换到接收机接收机操作的多媒体接口所需的耦合连接类型。

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