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1. 发明申请

US20030147416A1 Extendible asynchronous and synchronous interface bus for broadband access 失效
标题翻译：可扩展的异步和同步接口总线，用于宽带接入
公开(公告)号：US20030147416A1
公开(公告)日：2003-08-07
申请号：US10072329
申请日：2002-02-06
申请人： TranSwitch Corporation
发明人： John F. Gilsdorf , Yung-Yuan Yang
IPC分类号： H04L012/403
CPC分类号： H04L12/6418 , H04L2012/6435
摘要： Apparatus for simultaneously transferring synchronous and asynchronous signals among broadband access devices includes a data bus, a clock bus, and a plurality of control lines which are used to indicate the type of data being carried on the bus. According to the methods of the invention, data is transferred on the bus in a repeating frame having a plurality of slots, each slot being defined as one bus clock cycle. Each slot may contain a synchronous or asynchronous data signal and one or more of the control lines are asserted during the slot time of the data to indicate the type of data. Two embodiments are provided. One utilizes a 25 MHz clock bus and a repeating frame of three hundred thirty-six slots. The other utilizes a 75 MHz clock bus and a repeating frame of one thousand eight slots.
摘要翻译：用于在宽带接入设备之间同时传送同步和异步信号的设备包括数据总线，时钟总线以及用于指示在总线上承载的数据类型的多个控制线。根据本发明的方法，数据在具有多个时隙的重复帧中在总线上传送，每个时隙被定义为一个总线时钟周期。每个时隙可以包含同步或异步数据信号，并且在数据的时隙时间期间断言一个或多个控制线以指示数据的类型。提供了两个实施例。一个使用25MHz时钟总线和三百三十六个时隙的重复帧。另一个使用75MHz时钟总线和一千八个时隙的重复帧。

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