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1. 发明授权

US08150186B2 Amount-of-compressed data control method and image data compressing apparatus 失效
标题翻译：数据压缩数据控制方法和图像数据压缩装置
公开(公告)号：US08150186B2
公开(公告)日：2012-04-03
申请号：US11946582
申请日：2007-11-28
申请人： Masanori Imata , Toshihiko Hirose , Michio Hirai
发明人： Masanori Imata , Toshihiko Hirose , Michio Hirai
IPC分类号： G06K9/36
CPC分类号： H04N19/192 , H04N19/126 , H04N19/149 , H04N19/15 , H04N19/176 , H04N19/60
摘要： An amount-of-compressed-data control method applicable to image data compression processing for compressing an amount of data is disclosed. The method includes the steps of: performing quantization by: dividing one digital image into multiple blocks each having n×n pixels; performing orthogonal transform on each block; and dividing n×n conversion coefficients resulting from the conversion by each threshold value of a quantization matrix including n×n threshold values each resulting from the multiplication of a predetermined coefficient S (where S is a positive real number); and variable-length encoding the quantized data. In this method, the value of the coefficient S allows the amount of compressed data to fit within a predetermined range of a target amount of data by performing the quantization and encoding by dividing the interval that the coefficient S can take on into multiple intervals and calculating the estimated value of the coefficient S based on the relationship between the amount of compressed image data and the coefficient S, which is defined for each of the divided intervals.
摘要翻译：公开了一种适用于压缩数据量的图像数据压缩处理的压缩数据量控制方法。该方法包括以下步骤：通过以下步骤执行量化：将一个数字图像分成多个具有n×n个像素的块; 对每个块执行正交变换; 并且将由转换得到的n×n个转换系数除以由预定系数S（其中S是正实数）的乘法产生的n×n个阈值的量化矩阵的每个阈值。并对量化数据进行可变长度编码。在该方法中，系数S的值通过将系数S可以进行的间隔除以多个间隔进行量化和编码，从而将压缩数据量拟合到目标数据量的预定范围内，并计算基于压缩图像数据量与系数S之间的关系的系数S的估计值，这是针对每个划分的间隔定义的。

2. 发明申请

US20080131015A1 Amount-of-Compressed Data Control Method and Image Data Compressing Apparatus 失效
标题翻译：数据压缩数据控制方法和图像数据压缩装置
公开(公告)号：US20080131015A1
公开(公告)日：2008-06-05
申请号：US11946582
申请日：2007-11-28
申请人： Masanori Imata , Toshihiko Hirose , Michio Hirai
发明人： Masanori Imata , Toshihiko Hirose , Michio Hirai
IPC分类号： G06K9/36
CPC分类号： H04N19/192 , H04N19/126 , H04N19/149 , H04N19/15 , H04N19/176 , H04N19/60
摘要： An amount-of-compressed-data control method applicable to image data compression processing for compressing an amount of data is disclosed. The method includes the steps of: performing quantization by: dividing one digital image into multiple blocks each having n×n pixels; performing orthogonal transform on each block; and dividing n×n conversion coefficients resulting from the conversion by each threshold value of a quantization matrix including n×n threshold values each resulting from the multiplication of a predetermined coefficient S (where S is a positive real number); and variable-length encoding the quantized data. In this method, the value of the coefficient S allows the amount of compressed data to fit within a predetermined range of a target amount of data by performing the quantization and encoding by dividing the interval that the coefficient S can take on into multiple intervals and calculating the estimated value of the coefficient S based on the relationship between the amount of compressed image data and the coefficient S, which is defined for each of the divided intervals.
摘要翻译：公开了一种适用于压缩数据量的图像数据压缩处理的压缩数据量控制方法。该方法包括以下步骤：通过以下步骤执行量化：将一个数字图像分成多个具有n×n个像素的块; 对每个块执行正交变换; 并且将由转换得到的n×n转换系数除以由预定系数S（其中S是正实数）的乘法产生的n×n个阈值的量化矩阵的每个阈值。并对量化数据进行可变长度编码。在该方法中，系数S的值通过将系数S可以进行的间隔除以多个间隔进行量化和编码，从而将压缩数据量拟合到目标数据量的预定范围内，并计算基于压缩图像数据量与系数S之间的关系的系数S的估计值，这是针对每个划分的间隔定义的。

3. 发明授权

US5726945A Semiconductor device with reduced power consumption and thin film transistor used in semiconductor memory device for achieving reduction in power consumption 失效
标题翻译：用于半导体存储器件中的功耗降低的半导体器件和用于实现功耗降低的薄膜晶体管
公开(公告)号：US5726945A
公开(公告)日：1998-03-10
申请号：US676596
申请日：1996-07-03
申请人： Motomu Ukita , Toshihiko Hirose , Shigeto Maegawa
发明人： Motomu Ukita , Toshihiko Hirose , Shigeto Maegawa
IPC分类号： H01L27/04 , G11C5/14 , H01L21/822 , H01L27/10
CPC分类号： G11C5/147 , Y10S257/904
摘要： An SRAM according to the present invention includes a voltage-down circuit and an internal circuit. The voltage-down circuit includes three resistors, two PMOS transistors and an NMOS transistor. One PMOS transistor directly applies an external power supply voltage to the internal circuit. The NMOS transistor applies a voltage obtained by reducing the external power supply voltage by a threshold voltage thereof to the internal circuit. The value of a predetermined voltage as a condition for switching such application of the voltage by the PMOS transistor and application of the voltage by the NMOS transistor is determined by the resistance ratio of the two resistors. Each of the three resistors is formed by a plurality of resistance elements of one kind. Thus, even if the process parameter varies, the ratio of the resistance values of the two resistors which determines the switching point can be kept constant, thereby preventing variation in switching point.
摘要翻译：根据本发明的SRAM包括降压电路和内部电路。降压电路包括三个电阻，两个PMOS晶体管和一个NMOS晶体管。一个PMOS晶体管直接将外部电源电压施加到内部电路。 NMOS晶体管将通过将外部电源电压降低到其内部电路的阈值电压来获得的电压。作为用于切换由PMOS晶体管施加电压并由NMOS晶体管施加电压的条件的预定电压的值由两个电阻器的电阻比确定。三个电阻器中的每一个由多个一种电阻元件形成。因此，即使过程参数变化，也可以将确定开关点的两个电阻器的电阻值的比率保持为一定，从而防止开关点的变化。

4. 发明授权

US5544105A Static semiconductor memory device having circuitry for lowering potential of bit lines at commencement of data writing 失效
标题翻译：具有用于在开始数据写入时降低位线的电位的电路的静态半导体存储器件
公开(公告)号：US5544105A
公开(公告)日：1996-08-06
申请号：US271691
申请日：1994-07-07
申请人： Toshihiko Hirose , Shigeki Ohbayashi , Setsu Kondo , Takashi Hayasaka , Yoshiyuki Fujino , Masayuki Iketani
发明人： Toshihiko Hirose , Shigeki Ohbayashi , Setsu Kondo , Takashi Hayasaka , Yoshiyuki Fujino , Masayuki Iketani
IPC分类号： G11C11/41 , G11C7/14 , G11C7/22 , G11C11/401 , G11C11/407 , G11C11/417 , G11C11/419 , G11C29/00 , G11C7/00
CPC分类号： G11C29/78 , G11C11/417 , G11C11/419 , G11C7/14 , G11C7/22
摘要： A delay circuit delays an internal write control signal by a prescribed time to a global write driver. The global write driver is enabled in response to the delayed write control signal received from the delay circuit, to drive a global write data bus in accordance with internal write data from an input buffer. A block write driver is enabled in response to an internal write control signal and a block selection signal, to drive a local write data bus in response to data on the global write data bus. A write gate connects a bit line to the local write data bus in response to a column selection signal. The delay circuit sets the output of the block write driver at a low level for a prescribed period, whereby a precharge potential of the bit line is reduced to reduce the potential amplitude of the bit line in data writing. An SRAM which operates at a high speed with an enlarged write recovery time margin is provided. SRAM also includes various arrangement for improving operating characteristics and reliability.
摘要翻译：延迟电路将内部写入控制信号延迟规定时间到全局写入驱动器。全局写入驱动器响应于从延迟电路接收的延迟的写入控制信号而使能，以根据来自输入缓冲器的内部写入数据驱动全局写入数据总线。响应于内部写入控制信号和块选择信号来使能块写入驱动器，以响应于全局写入数据总线上的数据驱动本地写入数据总线。写入门响应于列选择信号将位线连接到本地写数据总线。延迟电路将块写入驱动器的输出设定为低电平达规定的周期，从而降低位线的预充电电位以减小数据写入中位线的电位振幅。提供了一种以高速运行并具有放大的写恢复时间裕度的SRAM。 SRAM还包括用于改进操作特性和可靠性的各种布置。

5. 发明授权

US4988888A CMOS output circuit with intermediate potential setting means 失效
标题翻译：具有中间电位设定装置的CMOS输出电路
公开(公告)号：US4988888A
公开(公告)日：1991-01-29
申请号：US361725
申请日：1989-06-05
申请人： Toshihiko Hirose , Tomohisa Wada
发明人： Toshihiko Hirose , Tomohisa Wada
IPC分类号： G11C11/417 , G11C11/409 , H03K4/02 , H03K19/00 , H03K19/003 , H03K19/017
CPC分类号： H03K4/02 , H03K19/0013 , H03K19/00361 , H03K19/01742
摘要： In a semiconductor integrated circuit device, an output MOSFET circuit includes a first N-type MOSFET and a first P-type MOSFET. The output circuit is controlled by two different control signals having two different levels to provide a signal at an output terminal at a junction between the two MOSFETs. An intermediate potential setting circuit includes a second N-type MOSFET and a second P-type MOSFET, and is followed by the output MOSFET circuit. The intermediate potential setting circuit sets the potential of the output terminal to an intermediate potential in accordance with an intermediate potential setting signal applied to the intermediate potential setting circuit prior to variation of the output. With this structure comsumption is reduced and high speed operation is made possible.
摘要翻译：在半导体集成电路器件中，输出MOSFET电路包括第一N型MOSFET和第一P型MOSFET。输出电路由具有两个不同电平的两个不同的控制信号控制，以在两个MOSFET之间的结处的输出端提供信号。中间电位设定电路包括第二N型MOSFET和第二P型MOSFET，其后面是输出MOSFET电路。中间电位设定电路根据在输出变化之前施加到中间电位设定电路的中间电位设定信号，将输出端子的电位设定为中间电位。利用这种结构，消耗减少，并且高速操作成为可能。

6. 发明授权

US09300145B2 Wireless power transmission apparatus 有权
标题翻译：无线电力传输装置
公开(公告)号：US09300145B2
公开(公告)日：2016-03-29
申请号：US13016582
申请日：2011-01-28
申请人： Hisato Hirasaka , Toshiyuki Hirose , Toshihiko Hirose , Tetsuro Makise , Akira Itou
发明人： Hisato Hirasaka , Toshiyuki Hirose , Toshihiko Hirose , Tetsuro Makise , Akira Itou
IPC分类号： H01F27/42 , H02J5/00 , H02J17/00 , H04K1/10 , H04L29/06
CPC分类号： H02J50/10 , H02J5/005 , H02J17/00 , H02J50/12 , H02J50/80 , H04K1/10 , H04L63/0442 , H04L63/083 , H04W12/06 , Y04S40/24
摘要： A wireless power transmission apparatus includes: a transmitter that wirelessly transmits electric power; and a receiver that can receive, in a resonant relation with the transmitter, a transmission signal including the electric power transmitted from the transmitter, wherein the receiver includes a frequency variable unit that can change a reception resonant frequency; a detecting unit that detects reception power; and a control unit that controls the frequency variable unit to perform frequency adjustment such that the reception power detected by the detecting unit is maximized.
摘要翻译：无线电力传输装置包括：无线发射电力的发射机; 以及接收器，其可以与所述发射机以共振关系接收包括从所述发射机发送的电力的发送信号，其中所述接收机包括可以改变接收谐振频率的频率可变单元; 检测单元，检测接收功率; 以及控制单元，其控制所述频率可变单元进行频率调整，使得由所述检测单元检测到的接收功率最大化。

7. 发明申请

US20070270532A1 Polyvinyl Chloride Fiber and Process for Production Thereof 审中-公开
标题翻译：聚氯乙烯纤维及其生产工艺
公开(公告)号：US20070270532A1
公开(公告)日：2007-11-22
申请号：US11663472
申请日：2005-09-29
申请人： Yasuo Ishibashi , Toshihiko Hirose , Hiroshi Yokoyama
发明人： Yasuo Ishibashi , Toshihiko Hirose , Hiroshi Yokoyama
IPC分类号： D01F6/48 , C08K3/26 , C08K5/07 , C08K5/098 , C08L27/06 , D01D5/084
CPC分类号： A41G3/0083 , C08K5/07 , C08K5/098 , D01F1/10 , D01F6/10 , C08L27/06
摘要： The polyvinyl chloride-based fiber of the present invention is formed of a vinyl chloride-based resin composition obtained by blending, with respect to (a) 100 parts by weight of a vinyl chloride-based resin, (b) 0.1 parts by weight to 0.6 parts by weight of a hydrotalcite-based thermostabilizer, (c) 0.1 parts by weight to 0.5 parts by weight of β-diketone, (d) 0.2 parts by weight to 0.5 parts by weight of a calcium soap and a zinc soap, (e) 0.7 parts by weight to 1.7 parts by weight of a lubricant, and (f) 0.5 parts by weight to 5 parts by weight of a plasticizer. Thereby, the present invention provides a polyvinyl chloride-based fiber that has an excellent touch feeling as a fiber for hair, excellent transparency and a vivid color tone, and can be obtained by stable melt spinning with less occurrence of filament breakage.
摘要翻译：本发明的聚氯乙烯类纤维由氯乙烯系树脂组合物形成，该组合物相对于（a）100重量份氯乙烯系树脂，（b）0.1重量份〜 0.6重量份的水滑石类热稳定剂，（c）0.1重量份〜0.5重量份的β-二酮，（d）0.2重量份〜0.5重量份的钙皂和锌皂（ e）0.7重量份至1.7重量份的润滑剂，和（f）0.5重量份至5重量份的增塑剂。因此，本发明提供一种聚氯乙烯系纤维，其作为毛发用纤维具有优异的触感，优异的透明性和鲜明的色调，可以通过稳定的熔融纺丝得到，同时发生短丝破裂。

8. 发明申请

US20070265378A1 Polyvinyl Chloride Fiber Reduced in Initial Coloration 审中-公开
标题翻译：初始着色中聚氯乙烯纤维减少
公开(公告)号：US20070265378A1
公开(公告)日：2007-11-15
申请号：US11663467
申请日：2005-09-29
申请人： Toshiyuki Kawaguchi , Yuichi Ohyama , Toshihiko Hirose
发明人： Toshiyuki Kawaguchi , Yuichi Ohyama , Toshihiko Hirose
IPC分类号： C08K5/07 , A41G3/00 , D01F6/48
CPC分类号： C08K5/07 , A41G3/0083 , C08K5/098 , D01F1/10 , D01F6/48 , C08L27/06
摘要： The polyvinyl chloride-based fiber of the present invention is a polyvinyl chloride-based fiber formed of a vinyl chloride-based resin composition that is obtained by blending, with respect to 100 parts by weight of a mixture (a) containing 95 wt % to 50 wt % of a vinyl chloride-based resin and 5 wt % to 50 wt % of a chlorinated vinyl chloride resin, 0.5 parts by weight to 3 parts by weight of a hydrotalcite-based thermostabilizer (b), 0.5 parts by weight to 2 parts by weight of a metallic soap-based thermostabilizer (c), and 0.5 parts by weight to 1.2 parts by weight of β-diketone as a stabilizing aid (d). This polyvinyl chloride-based fiber has excellent spinnability, excellent transparency, small initial coloration and excellent colorability, and thus has a high commercial value as artificial hair for hair adornment, and can be used widely for practical goods and fashion purposes. Moreover, due to this property, the polyvinyl chloride-based fiber also can be applied to a field of industrial materials and the like besides artificial hair.
摘要翻译：本发明的聚氯乙烯系纤维是由氯乙烯系树脂组合物形成的聚氯乙烯系纤维，其相对于100重量份的含有95重量％以上的混合物（a）〜 50重量％的氯乙烯类树脂和5重量％〜50重量％的氯化氯乙烯树脂，0.5重量份〜3重量份的水滑石类热稳定剂（b），0.5重量份〜2重量％重量份的金属皂基热稳定剂（c）和0.5重量份至1.2重量份的作为稳定助剂的β-二酮（d）。该聚氯乙烯类纤维具有优异的可纺性，优异的透明性，初期着色性和着色性优异，作为头发装饰用的人造毛发具有高的商业价值，可广泛用于实用的商品和时尚用途。此外，由于该性能，聚氯乙烯系纤维也可以应用于除人造毛发以外的工业材料等领域。

9. 发明授权

US5946329A Viterbi decoding method and viterbi decoder 失效
标题翻译：维特比解码方法和维特比解码器
公开(公告)号：US5946329A
公开(公告)日：1999-08-31
申请号：US786209
申请日：1997-01-21
申请人： Toshihiko Hirose , Hiroyuki Ino
发明人： Toshihiko Hirose , Hiroyuki Ino
IPC分类号： H03M13/23 , G11B20/10 , H03M13/41 , G06F11/10
CPC分类号： H03M13/6502 , G11B20/10009 , H03M13/41
摘要： A Viterbi decoding method and decoder are provided for achieving a faster operation than the prior art. The Viterbi decoding method and decoder are arranged to determine the most approximate path on two-state state metrics and decode the data on the most approximate path. The Viterbi decoder includes registers 2 and 3 for reading two pieces of sample data, an adder 14 for adding two pieces of sample data read by the registers 2 and 3, and an arrangement located after the adder 14 for determining a path of each state transition by comparing the added result with a given identification of -1, 0 or 1.
摘要翻译：提供维特比解码方法和解码器以实现比现有技术更快的操作。维特比解码方法和解码器被布置成确定两状态状态度量上的最近路径，并对最近路径上的数据进行解码。维特比解码器包括用于读取两个采样数据的寄存器2和3，用于加上由寄存器2和3读取的两个采样数据的加法器14以及位于加法器14之后的用于确定每个状态转换的路径的配置通过比较添加的结果与-1,0或1的给定标识。

10. 发明授权

US5694354A Static random access memory device having a single bit line configuration 失效
标题翻译：具有单位线配置的静态随机存取存储器件
公开(公告)号：US5694354A
公开(公告)日：1997-12-02
申请号：US708063
申请日：1996-08-12
申请人： Kenji Anami , Toshihiko Hirose , Shuji Murakami , Kojiro Yuzuriha
发明人： Kenji Anami , Toshihiko Hirose , Shuji Murakami , Kojiro Yuzuriha
IPC分类号： G11C11/412 , G11C11/418 , G11C11/419 , H01L21/8244 , H01L27/11 , G11C11/00
CPC分类号： H01L27/11 , G11C11/412 , G11C11/418 , G11C11/419 , H01L27/1108
摘要： A static random access memory (SRAM) is disclosed having a single bit line configuration. One memory cell includes access gate transistors Q5, Q6 connected in series between a data storage circuit 1 and a single bit line BL. In a writing operation, the gate electrodes of the transistors Q5, Q6 are boosted to a level exceeding the supply voltage by a X word line boosting circuit 7 and a Y word line boosting circuit 8 to bring the data storage circuit to an unstable data storage state in a memory cell selected by a row address signal and a column address signal. Data writing is carried out only in a desired memory cell, and erroneous data writing to other memory cells is prevented.
摘要翻译：公开了具有单个位线配置的静态随机存取存储器（SRAM）。一个存储单元包括串联连接在数据存储电路1和单个位线BL之间的存取栅极晶体管Q5，Q6。在写入操作中，晶体管Q5，Q6的栅电极通过X字线升压电路7和Y字线升压电路8升压到超过电源电压的电平，以使数据存储电路处于不稳定的数据存储状态在由行地址信号和列地址信号选择的存储单元中。仅在期望的存储单元中执行数据写入，并且防止对其它存储单元的错误数据写入。

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