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1. 发明授权

US5506805A Static semiconductor memory device having circuitry for enlarging write recovery margin 失效
标题翻译：具有放大写恢复余量的电路的静态半导体存储器件
公开(公告)号：US5506805A
公开(公告)日：1996-04-09
申请号：US402212
申请日：1995-03-10
申请人： Toshihiko Hirose , Shigeki Ohbayashi , Setsu Kondo , Takashi Hayasaka , Yoshiyuki Fujino , Masayuki Iketani
发明人： Toshihiko Hirose , Shigeki Ohbayashi , Setsu Kondo , Takashi Hayasaka , Yoshiyuki Fujino , Masayuki Iketani
IPC分类号： G11C11/41 , G11C7/14 , G11C7/22 , G11C11/401 , G11C11/407 , G11C11/417 , G11C11/419 , G11C29/00 , G11C7/00
CPC分类号： G11C29/78 , G11C11/417 , G11C11/419 , G11C7/14 , G11C7/22
摘要： A delay circuit delays an internal write control signal by a prescribed time to a global write driver. The global write driver is enabled in response to the delayed write control signal received from the delay circuit, to drive a global write data bus in accordance with internal write data from an input buffer. A block write driver is enabled in response to an internal write control signal and a block selection signal, to drive a local write data bus in response to data on the global write data bus. A write gate connects a bit line to the local write data bus in response to a column selection signal. The delay circuit sets the output of the block write driver at a low level for a prescribed period, whereby a precharge potential of the bit line is reduced to reduce the potential amplitude of the bit line in data writing. An SRAM which operates at a high speed with an enlarged write recovery time margin is provided. SRAM also includes various arrangement for improving operating characteristics and reliability.
摘要翻译：延迟电路将内部写入控制信号延迟规定时间到全局写入驱动器。全局写入驱动器响应于从延迟电路接收的延迟的写入控制信号而使能，以根据来自输入缓冲器的内部写入数据驱动全局写入数据总线。响应于内部写入控制信号和块选择信号来使能块写入驱动器，以响应于全局写入数据总线上的数据驱动本地写入数据总线。写入门响应于列选择信号将位线连接到本地写数据总线。延迟电路将块写入驱动器的输出设定为低电平达规定的周期，从而降低位线的预充电电位以减小数据写入中位线的电位振幅。提供了一种以高速运行并具有放大的写恢复时间裕度的SRAM。 SRAM还包括用于改善操作特性和可靠性的各种布置。

2. 发明授权

US5544105A Static semiconductor memory device having circuitry for lowering potential of bit lines at commencement of data writing 失效
标题翻译：具有用于在开始数据写入时降低位线的电位的电路的静态半导体存储器件
公开(公告)号：US5544105A
公开(公告)日：1996-08-06
申请号：US271691
申请日：1994-07-07
申请人： Toshihiko Hirose , Shigeki Ohbayashi , Setsu Kondo , Takashi Hayasaka , Yoshiyuki Fujino , Masayuki Iketani
发明人： Toshihiko Hirose , Shigeki Ohbayashi , Setsu Kondo , Takashi Hayasaka , Yoshiyuki Fujino , Masayuki Iketani
IPC分类号： G11C11/41 , G11C7/14 , G11C7/22 , G11C11/401 , G11C11/407 , G11C11/417 , G11C11/419 , G11C29/00 , G11C7/00
CPC分类号： G11C29/78 , G11C11/417 , G11C11/419 , G11C7/14 , G11C7/22
摘要： A delay circuit delays an internal write control signal by a prescribed time to a global write driver. The global write driver is enabled in response to the delayed write control signal received from the delay circuit, to drive a global write data bus in accordance with internal write data from an input buffer. A block write driver is enabled in response to an internal write control signal and a block selection signal, to drive a local write data bus in response to data on the global write data bus. A write gate connects a bit line to the local write data bus in response to a column selection signal. The delay circuit sets the output of the block write driver at a low level for a prescribed period, whereby a precharge potential of the bit line is reduced to reduce the potential amplitude of the bit line in data writing. An SRAM which operates at a high speed with an enlarged write recovery time margin is provided. SRAM also includes various arrangement for improving operating characteristics and reliability.
摘要翻译：延迟电路将内部写入控制信号延迟规定时间到全局写入驱动器。全局写入驱动器响应于从延迟电路接收的延迟的写入控制信号而使能，以根据来自输入缓冲器的内部写入数据驱动全局写入数据总线。响应于内部写入控制信号和块选择信号来使能块写入驱动器，以响应于全局写入数据总线上的数据驱动本地写入数据总线。写入门响应于列选择信号将位线连接到本地写数据总线。延迟电路将块写入驱动器的输出设定为低电平达规定的周期，从而降低位线的预充电电位以减小数据写入中位线的电位振幅。提供了一种以高速运行并具有放大的写恢复时间裕度的SRAM。 SRAM还包括用于改进操作特性和可靠性的各种布置。

3. 发明授权

US5515326A Static semiconductor memory device having circuitry for lowering potential of bit lines at commencement of data writing 失效
公开(公告)号：US5515326A
公开(公告)日：1996-05-07
申请号：US402221
申请日：1995-03-10
申请人： Toshihiko Hirose , Shigeki Ohbayashi , Setsu Kondo , Takashi Hayasaka , Yoshiyuki Fujino , Masayuki Iketani
发明人： Toshihiko Hirose , Shigeki Ohbayashi , Setsu Kondo , Takashi Hayasaka , Yoshiyuki Fujino , Masayuki Iketani
IPC分类号： G11C11/41 , G11C7/14 , G11C7/22 , G11C11/401 , G11C11/407 , G11C11/417 , G11C11/419 , G11C29/00 , G11C7/00
CPC分类号： G11C29/78 , G11C11/417 , G11C11/419 , G11C7/14 , G11C7/22
摘要： A delay circuit delays an internal write control signal by a prescribed time to a global write driver. The global write driver is enabled in response to the delayed write control signal received from the delay circuit, to drive a global write data bus in accordance with internal write data from an input buffer. A block write driver is enabled in response to an internal write control signal and a block selection signal, to drive a local write data bus in response to data on the global write data bus. A write gate connects a bit line to the local write data bus in response to a column selection signal. The delay circuit sets the output of the block write driver at a low level for a prescribed period, whereby a precharge potential of the bit line is reduced to reduce the potential amplitude of the bit line in data writing. An SRAM which operates at a high speed with an enlarged write recovery time margin is provided. SRAM also includes various arrangement for improving operating characteristics and reliability.

4. 发明授权

US5659513A Static semiconductor memory device having improved characteristics 失效
标题翻译：具有改进特性的静态半导体存储器件
公开(公告)号：US5659513A
公开(公告)日：1997-08-19
申请号：US526245
申请日：1995-09-11
申请人： Toshihiko Hirose , Shigeki Ohbayashi , Setsu Kondo , Takashi Hayasaka , Yoshiyuki Fujino , Masayuki Iketani
发明人： Toshihiko Hirose , Shigeki Ohbayashi , Setsu Kondo , Takashi Hayasaka , Yoshiyuki Fujino , Masayuki Iketani
IPC分类号： G11C11/41 , G11C7/14 , G11C7/22 , G11C11/401 , G11C11/407 , G11C11/417 , G11C11/419 , G11C29/00 , G05F3/24
CPC分类号： G11C29/78 , G11C11/417 , G11C11/419 , G11C7/14 , G11C7/22
摘要： A delay circuit delays an internal write control signal by a prescribed time to a global write driver. The global write driver is enabled in response to the delayed write control signal received from the delay circuit, to drive a global write data bus in accordance with internal write data from an input buffer. A block write driver is enabled in response to an internal write control signal and a block selection signal, to drive a local write data bus in response to data on the global write data bus. A write gate connects a bit line to the local write data bus in response to a column selection signal. The delay circuit sets the output of the block write driver at a low level for a prescribed period, whereby a precharge potential of the bit line is reduced to reduce the potential amplitude of the bit line in data writing. An SRAM which operates at a high speed with an enlarged write recovery time margin is provided. SRAM also includes various arrangement for improving operating characteristics and reliability.
摘要翻译：延迟电路将内部写入控制信号延迟规定时间到全局写入驱动器。全局写入驱动器响应于从延迟电路接收的延迟的写入控制信号而使能，以根据来自输入缓冲器的内部写入数据驱动全局写入数据总线。响应于内部写入控制信号和块选择信号来使能块写入驱动器，以响应于全局写入数据总线上的数据驱动本地写入数据总线。写入门响应于列选择信号将位线连接到本地写数据总线。延迟电路将块写入驱动器的输出设定为低电平达规定的周期，从而降低位线的预充电电位以减小数据写入中位线的电位振幅。提供了一种以高速运行并具有放大的写恢复时间裕度的SRAM。 SRAM还包括用于改善操作特性和可靠性的各种布置。

5. 发明授权

US5629900A Semiconductor memory device operable to write data accurately at high speed 失效
标题翻译：半导体存储器件可操作以高速准确地写入数据
公开(公告)号：US5629900A
公开(公告)日：1997-05-13
申请号：US526247
申请日：1995-09-11
申请人： Toshihiko Hirose , Shigeki Ohbayashi , Setsu Kondo , Takashi Hayasaka , Yoshiyuki Fujino , Masayuki Iketani
发明人： Toshihiko Hirose , Shigeki Ohbayashi , Setsu Kondo , Takashi Hayasaka , Yoshiyuki Fujino , Masayuki Iketani
IPC分类号： G11C11/41 , G11C7/14 , G11C7/22 , G11C11/401 , G11C11/407 , G11C11/417 , G11C11/419 , G11C29/00 , G11C7/00
CPC分类号： G11C29/78 , G11C11/417 , G11C11/419 , G11C7/14 , G11C7/22
摘要： A delay circuit delays an internal write control signal by a prescribed time to a global write driver. The global write driver is enabled in response to the delayed write control signal received from the delay circuit, to drive a global write data bus in accordance with internal write data from an input buffer. A block write driver is enabled in response to an internal write control signal and a block selection signal, to drive a local write data bus in response to data on the global write data bus. A write gate connects a bit line to the local write data bus in response to a column selection signal. The delay circuit sets the output of the block write driver at a low level for a prescribed period, whereby a precharge potential of the bit line is reduced to reduce the potential amplitude of the bit line in data writing. An SRAM which operates at a high speed with an enlarged write recovery time margin is provided. SRAM also includes various arrangement for improving operating characteristics and reliability.
摘要翻译：延迟电路将内部写入控制信号延迟规定时间到全局写入驱动器。全局写入驱动器响应于从延迟电路接收的延迟的写入控制信号而使能，以根据来自输入缓冲器的内部写入数据驱动全局写入数据总线。响应于内部写入控制信号和块选择信号来使能块写入驱动器，以响应于全局写入数据总线上的数据驱动本地写入数据总线。写入门响应于列选择信号将位线连接到本地写数据总线。延迟电路将块写入驱动器的输出设定为低电平达规定的周期，从而降低位线的预充电电位以减小数据写入中位线的电位振幅。提供了一种以高速运行并具有放大的写恢复时间裕度的SRAM。 SRAM还包括用于改善操作特性和可靠性的各种布置。

6. 发明授权

US5491655A Semiconductor memory device having non-selecting level generation circuitry for providing a low potential during reading mode and high level potential during another operation mode 失效
标题翻译：具有非选择电平生成电路的半导体存储器件，用于在读取模式期间提供低电位，在另一个操作模式期间具有高电平电位
公开(公告)号：US5491655A
公开(公告)日：1996-02-13
申请号：US402218
申请日：1995-03-10
申请人： Toshihiko Hirose , Shigeki Ohbayashi , Setsu Kondo , Takashi Hayasaka , Yoshiyuki Fujino , Masayuki Iketani
发明人： Toshihiko Hirose , Shigeki Ohbayashi , Setsu Kondo , Takashi Hayasaka , Yoshiyuki Fujino , Masayuki Iketani
IPC分类号： G11C11/41 , G11C7/14 , G11C7/22 , G11C11/401 , G11C11/407 , G11C11/417 , G11C11/419 , G11C29/00 , G11C7/00
CPC分类号： G11C29/78 , G11C11/417 , G11C11/419 , G11C7/14 , G11C7/22
摘要： A semiconductor memory device has a plurality of memory cells arranged in rows and columns, a plurality of pairs of complementary first and second bit lines arranged corresponding to respective columns and connecting memory cells on a corresponding column, first and second read data lines, and a plurality of pairs of first and second bipolar transistor provided for respective pairs of first and second bit lines. Each first bipolar transistor is coupled to the first read data line and each second bipolar transistor is coupled to the second read data line and a plurality of first switching circuits transfer potentials of the first and second bit lines to respective bases of corresponding first and second bipolar transistors. A reference line transmits a non-selection level voltage and a plurality of second switching circuits, operating complementary to the corresponding first switching circuits, transfer the non-selection level voltage to bases of corresponding first and second bipolar transistors. Generator circuitry generates non-selection level voltage having (i) a potential level lower than or equal to a low level potential of a selected bit line in a data reading operation mode and (ii) a potential level higher than or equal to a high level potential of the selected bit line in an operation mode other than the data reading operation mode.
摘要翻译：半导体存储器件具有排列成行和列的多个存储单元，对应于相应列而排列的多对互补的第一和第二位线，并将相应列上的存储单元，第一和第二读取数据线以及多对成对的第一和第二双极晶体管被提供用于各对第一和第二位线。每个第一双极晶体管耦合到第一读取数据线，并且每个第二双极晶体管耦合到第二读取数据线，并且多个第一开关电路将第一和第二位线的电位转移到相应的第一和第二双极的相应基极晶体管。参考线发送非选择电平电压和与对应的第一开关电路互补的多个第二开关电路，将非选择电平电压传送到对应的第一和第二双极晶体管的基极。发电机电路产生非选择电平电压，其具有（i）在数据读取操作模式中低于或等于所选位线的低电平电位的电位电平，以及（ii）高于或等于高电平的电位电平在除数据读取操作模式之外的操作模式中所选位线的电位。

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