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    • 1. 发明授权
    • Method of manufacturing semiconductor device
    • 制造半导体器件的方法
    • US06867139B2
    • 2005-03-15
    • US10164130
    • 2002-06-05
    • Tomoko Wake
    • Tomoko Wake
    • H01L21/3205H01L21/304H01L21/321H01L21/768H01L21/302
    • H01L21/7684H01L21/3212
    • A semiconductor device manufacturing method wherein a via-hole is formed in an second inter-layer insulating film covering a lower layer wiring, throughout a surface of which are then formed a barrier film made of Ta (tantalum) and a Cu (copper) film sequentially, after which, first an unnecessary part of the Cu film is removed by a CMP (Chemical Mechanical Polishing) method using such a polishing liquid to which hydrogen peroxide is added by 1.5 weight-percent or more (first polishing step) and then an unnecessary part of the barrier film is removed by a CMP method for using a polishing liquid to which hydrogen peroxide is added by 0.09-1.5 weight-percent and applying a pressure of 4-10 Psi (pounds per square inch) on the barrier film (second polishing step).
    • 一种半导体器件制造方法,其中在覆盖下层布线的第二层间绝缘膜中形成通孔,然后在其整个表面形成由Ta(钽)和Cu(铜)膜制成的阻挡膜 之后,首先通过使用加入过氧化氢的这种研磨液的CMP(化学机械抛光)法除去1.5重量%以上的(第一研磨工序)的Cu膜的不必要部分, 通过使用加入过氧化氢的抛光液0.09-1.5重量%并施加4-10Psi(磅/平方英寸)的压力在阻挡膜上的CMP方法除去不需要的部分阻挡膜 第二抛光步骤)。
    • 3. 发明授权
    • Process for forming a metal interconnect
    • 用于形成金属互连的工艺
    • US06930037B2
    • 2005-08-16
    • US09737397
    • 2000-12-15
    • Yasuaki TsuchiyaTomoko Wake
    • Yasuaki TsuchiyaTomoko Wake
    • B24B37/00C09K3/00H01L21/304H01L21/3205H01L21/321H01L21/768H01L23/532H01L21/4763
    • H01L21/7684H01L23/53228H01L2924/0002Y10S438/959H01L2924/00
    • This invention relates to a process for forming a metal interconnect comprising the steps of forming a concave in an insulating film formed on a substrate, forming a barrier metal film on the insulating film, forming an interconnect metal film over the whole surface such that the concave is filled with the metal and then polishing the surface of the substrate by chemical mechanical polishing, characterized in that the polishing step comprises a first polishing step of polishing the surface such that the interconnect metal film partially remains on the surface other than the concave and a second polishing step of polishing the surface using a polishing slurry controlling a polishing-rate ratio of the interconnect metal to the barrier metal to 1 to 3 both inclusive, until the surface of the insulating film other than the concave is substantially completely exposed. According to this invention, dishing and erosion can be prevented and a reliable damascene interconnect with a small dispersion of an interconnect resistance can be formed.
    • 本发明涉及一种用于形成金属互连的方法,包括以下步骤:在形成在基板上的绝缘膜中形成凹陷,在绝缘膜上形成阻挡金属膜,在整个表面上形成互连金属膜, 填充金属,然后通过化学机械抛光抛光衬底的表面,其特征在于抛光步骤包括抛光表面的第一抛光步骤,使得互连金属膜部分地保留在除了凹部以外的表面上,以及 使用将互连金属与阻挡金属的研磨速度比控制在1〜3之间的抛光浆料将表面进行研磨的第二研磨工序,直到除凹部以外的绝缘膜的表面基本上完全露出。 根据本发明,可以防止凹陷和侵蚀,并且可以形成可靠的镶嵌与互连电阻的小分散的互连。
    • 4. 发明授权
    • Cleaning-apparatus line configuration and designing process therefor
    • 清洗设备线路配置及设计流程
    • US06725119B1
    • 2004-04-20
    • US09661192
    • 2000-09-13
    • Tomoko Wake
    • Tomoko Wake
    • G06F1900
    • H01L21/67253H01L21/02063Y10S134/902Y10S438/906
    • An objective of this invention is to provide a process for selecting rationally and quickly a wet process treatment in which an etchant can be shared based on a minimum preliminary investigation while eliminating cross contamination derived from a newly employed material, in a cleaning-apparatus line configuration in a process for manufacturing a silicon semiconductor device. In advance, an element which is suspected to cause cross contamination is added to an etchant used in a wet processing, a silicon substrate is immersed in the etchant, and then a correlation between a concentration of the element adhesively remaining still on the surface of the silicon substrate after the etchant is washed out with water and a concentration of the dissolved element in the etchant. On the basis of the result, the upper concentration limit of the element remaining by cross contamination is estimated when sharing the etchant. Then, with reference to the upper limit, whether deterioration of device properties occurs is evaluated to determine acceptability of etchant sharing.
    • 本发明的目的是提供一种选择合理且快速地选择湿法处理的方法,其中可以在清除装置线配置中基于最初的初步调查同时消除来自新使用的材料的交叉污染而共享蚀刻剂 在制造硅半导体器件的过程中。 预先将被怀疑引起交叉污染的元素添加到用于湿法处理的蚀刻剂中,将硅衬底浸入蚀刻剂中,然后将元素的浓度仍然保持在表面上的相关性 蚀刻剂用水洗涤后的硅衬底以及溶解元素在蚀刻剂中的浓度。 在结果的基础上,当共享蚀刻剂时,估计交叉污染物剩余元素的浓度上限。 然后,参照上限,评价是否发生器件特性的劣化,以确定蚀刻剂共享的可接受性。
    • 5. 发明授权
    • Method of forming a copper-containing metal interconnect using a chemical mechanical planarization (CMP) slurry
    • 使用化学机械平坦化(CMP)浆料形成含铜金属互连的方法
    • US06436811B1
    • 2002-08-20
    • US09741131
    • 2000-12-19
    • Tomoko WakeYasuaki Tsuchiya
    • Tomoko WakeYasuaki Tsuchiya
    • H01L214763
    • C09G1/02H01L21/3212H01L21/7684
    • This invention relates to a process for forming a metal interconnect comprising the steps of forming a concave in an insulating film formed on a substrate, forming a copper-containing metal film over the whole surface such that the concave is filled with the metal and then polishing the copper-containing metal film by chemical mechanical polishing, characterized in that the polishing step is conducted using a chemical mechanical polishing slurry comprising a polishing material, an oxidizing agent and an adhesion inhibitor preventing adhesion of a polishing product to a polishing pad, while contacting the polishing pad to a polished surface with a pressure of at least 27 kPa. This invention allows us to prevent adhesion of a polishing product to a polishing pad and to form a uniform interconnect layer with an improved throughput, even when polishing a large amount of copper-containing metal during a polishing step.
    • 本发明涉及一种用于形成金属互连的方法,包括以下步骤:在形成在基板上的绝缘膜中形成凹陷,在整个表面上形成含铜金属膜,使得凹入物被金属填充,然后抛光 通过化学机械抛光的含铜金属膜,其特征在于,使用包含抛光材料,氧化剂和防粘附剂的化学机械抛光浆料进行抛光步骤,防止抛光产品粘附到抛光垫上,同时接触 该抛光垫至少压力为27kPa的抛光表面。 本发明允许我们防止抛光产品与抛光垫的粘合,并且即使在抛光步骤中抛光大量含铜金属时,也能够提高生产能力,形成均匀的互连层。