专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5404448A Multi-pixel access memory system 失效
标题翻译：多像素存取存储器系统
公开(公告)号：US5404448A
公开(公告)日：1995-04-04
申请号：US264420
申请日：1994-06-23
申请人： Andrew D. Bowen , Timothy J. Ebbers , Randall L. Henderson
发明人： Andrew D. Bowen , Timothy J. Ebbers , Randall L. Henderson
IPC分类号： G06F12/02 , G06T1/60 , G06F15/62
CPC分类号： G06T1/60 , G06F12/0207
摘要： A random access memory system organized such that multiple pixels may be accessed when one row column address is provided. The random access memory system includes a first group of random access memory devices and a second group of random access memory devices. The first group of devices stores information for pixels on an even horizontal scan line and the second group of devices stores information for pixels on an odd horizontal scan line. An address generator of the random access memory system generates an address to access information from the first group of devices for one pixel and information from the second group of devices for another pixel.
摘要翻译：组织的随机存取存储器系统，使得当提供一个行列地址时可以访问多个像素。随机存取存储器系统包括第一组随机存取存储器件和第二组随机存取存储器件。第一组装置存储偶数水平扫描线上像素的信息，第二组装置存储奇数水平扫描线上的像素信息。随机存取存储器系统的地址生成器生成一个地址以访问来自第一组装置的一个像素的信息和来自第二组装置的信息用于另一个像素。

2. 发明授权

US5255359A Picking function for a pipeline graphics system using hierarchical graphics structures 失效
标题翻译：采用分层图形结构的管道图形系统的采集功能
公开(公告)号：US5255359A
公开(公告)日：1993-10-19
申请号：US425781
申请日：1989-10-23
申请人： Timothy J. Ebbers , Daniel G. Gibbons , David W. Li , Bob C. Liang , David C. Tannenbaum
发明人： Timothy J. Ebbers , Daniel G. Gibbons , David W. Li , Bob C. Liang , David C. Tannenbaum
IPC分类号： G06T11/00 , G06F3/033 , G06F3/048 , G06T11/80 , G06T17/00 , G06F3/153
CPC分类号： G06T17/00 , G06F3/04842
摘要： A graphics display system picking function tracks machine states of pickable primitive operators through the use of a pick stack and machine state memory. The pick stack operates as a stack when accessed by pipeline processors. Pipeline processors can add an element to the stack or remove elements from the stack as structures are processed. Selection or picking of an object causes a graphics control processor to randomly access the pick stack to determine the attributes of a picked primitive. The machine state memory is implemented as a video RAM allowing rapid copying of rows containing machine states for various structure levels in the hierarchy. A first area of the machine state memory stores the states relating to the structures in the hierarchy as they are executed. A second area retains an abbreviated state description for each pickable primitive while a final area contains abbreviated machine state information for picked objects to be echoed by the system. The pick stack and machine state memories operate together to provide rapid pick identification, picked primitive machine state identification, and picked primitive echoing. The use of separate picked primitive echo machine storage allows drawing of the picked primitives without a complete re-traversal of the displayed list. This also results in reduced processing time.

3. 发明授权

US5119477A Memory manager for hierarchical graphic structures 失效
标题翻译：分层图形结构的记忆管理员
公开(公告)号：US5119477A
公开(公告)日：1992-06-02
申请号：US425764
申请日：1989-10-23
申请人： Timothy J. Ebbers
发明人： Timothy J. Ebbers
IPC分类号： G06T1/00 , G06T11/00 , G06T17/00
CPC分类号： G06T17/00
摘要： Video random access memory having a random array and serial buffer is employed to speed the replication of structure state information used in the processing of hierarchical graphic data structures. Specialized circuitry in the video RAM and associated VRAM sequencer are used to perform a rapid transfer of structure state information from one row of the VRAM (the parent row) to a second VRAM row (the child row). The VRAM sequencer is modified to perform back to back read data transfer and write data transfer operation in response to a single graphics processor command. The return to previous structure state can be accomplished by readdressing the VRAM row containing the previous structure state.

4. 发明授权

US5001672A Video ram with external select of active serial access register 失效
标题翻译：视频RAM与外部选择有源串行访问寄存器
公开(公告)号：US5001672A
公开(公告)日：1991-03-19
申请号：US352802
申请日：1989-05-16
申请人： Timothy J. Ebbers , Satish Gupta , Randall L. Henderson , Nathan R. Hiltebeitel , Robert Tamlyn , Steven W. Tomashot , Todd Williams
发明人： Timothy J. Ebbers , Satish Gupta , Randall L. Henderson , Nathan R. Hiltebeitel , Robert Tamlyn , Steven W. Tomashot , Todd Williams
IPC分类号： G11C11/401 , G11C7/10
CPC分类号： G11C7/1075
摘要： An implementation of a serial access memory register facility which allows the external selection of the portion of the SAM to be scanned out. A control signal is provided which causes the reloading of serial access memory address counter causing the reloading of serial access memory address counter causing the serial scanning to shift from one to another of the serial access memory registers. The result is an ability to select a stopping point when scanning out of the serial access memory. Thus, the present invention implements the ability in a video random access memory to specify both the starting and ending points of the data to be scanned out of the serial access memory. The preferred embodiment replaces the QSF status pin with a control pin to preserve the packaging configuration of standard VRAMs.

5. 发明授权

US5148521A Pick data queue for pipelined graphics system 失效
标题翻译：用于管道图形系统的PICK数据队列
公开(公告)号：US5148521A
公开(公告)日：1992-09-15
申请号：US425776
申请日：1989-10-23
申请人： Timothy J. Ebbers , Daniel G. Gibbons
发明人： Timothy J. Ebbers , Daniel G. Gibbons
IPC分类号： G06T11/80 , G06T17/00
CPC分类号： G06T17/00
摘要： A pick queue and pick detection method that allows non-hierarchical graphic data models and applications to be used with pipelined processing systems. Pretransformed formatting logic is placed prior to pipeline processors to store necessary picking information in a pick queue. A pick tag addressing the pick queue is passed with each graphics order through the pipeline and stored in the pick detect logic. The pick detect logic interrupts the graphics control processor that then accesses the tag register associated with the graphics order and the coordinate counter to address the stored pick information of the order triggering the pick. The graphics processor uses the tag address and coordinate counter to indirectly address the pick queue and retrieve the information that needs to be passed back to the application program. The structure eliminates the requirement to pass all information through the pipeline processors.

6. 发明授权

US5257237A SAM data selection on dual-ported DRAM devices 失效
标题翻译：双端口DRAM设备上的SAM数据选择
公开(公告)号：US5257237A
公开(公告)日：1993-10-26
申请号：US791666
申请日：1991-11-12
申请人： Michael A. Aranda , Andrew D. Bowen , Timothy J. Ebbers , Randall L. Henderson , Nathan R. Hiltebeitel , Robert Tamlyn
发明人： Michael A. Aranda , Andrew D. Bowen , Timothy J. Ebbers , Randall L. Henderson , Nathan R. Hiltebeitel , Robert Tamlyn
IPC分类号： G11C7/10 , G11C8/00 , G11C11/4096
CPC分类号： G11C11/4096 , G11C7/1075 , G11C8/00
摘要： The selection in a dual port memory device of data from a serial access memory register having a lower byte and an upper byte of data is described herein. In one embodiment, the register is partitioned lengthwise into two sections, corresponding to, for example, a frame buffer A and a frame buffer B. On each serial clock cycle, frame buffer A or frame buffer B for each byte of data may be selected from the register. Each of the selected bytes of data are then passed to a serial output port. In another embodiment, the lower byte of data corresponds to, for example, a frame buffer A and the upper byte corresponds to a frame buffer B. Then either the upper byte or lower byte of data is selected to be output on the serial port. In yet a further embodiment, the serial access memory register is partitioned lengthwise into two sections, each section corresponding to, for example, a frame buffer and the bytes of data correspond to another buffer, then either the lower byte or upper byte is selected to be output on the serial port.
摘要翻译：这里描述了具有低字节和高字节数据的串行访问存储器寄存器的双端口存储器件中的数据的选择。在一个实施例中，寄存器被纵向分割成对应于例如帧缓冲器A和帧缓冲器B的两个部分。在每个串行时钟周期上，可以选择每个数据字节的帧缓冲器A或帧缓冲器B 从登记册。然后将每个选定的数据字节传递给串行输出端口。在另一个实施例中，数据的低字节对应于例如帧缓冲器A，高字节对应于帧缓冲器B.然后选择数据的高字节或低字节在串行端口上输出。在又一个实施例中，串行访问存储器寄存器被纵向划分为两个部分，每个部分对应于例如帧缓冲器，并且数据字节对应于另一个缓冲器，则低字节或高字节被选择为在串口上输出。

7. 发明授权

US4878182A Multiple pixel generator 失效
标题翻译：多像素发生器
公开(公告)号：US4878182A
公开(公告)日：1989-10-31
申请号：US115451
申请日：1987-10-30
申请人： Michael A. Aranda , Timothy J. Ebbers , Yoshio Iida , Terence W. Lindgren , Taggart H. Robertson
发明人： Michael A. Aranda , Timothy J. Ebbers , Yoshio Iida , Terence W. Lindgren , Taggart H. Robertson
IPC分类号： G06T11/20
CPC分类号： G06T11/203
摘要： A system for generating multiple pixels in a single machine cycle employs a plurality of parallel vector generators. Each of the parallel generators is initialized with an error term which is calcualted in accordance with Bresenham's algorithm. The signs of these error terms are then used to determine the region within the first octant of the coordinate system which contains the function for which the pixels are to be generated. The region data, in turn, determine two selectable values for an increment which is to be added to a running error term for each of the parallel generators as multiple pixels are simultaneously generated. The choice of the two possible values to be added to the error term is dependent upon the sign of the error term itself. The sign of the running error term for each vector generator is utilized to form a sequence of binary data which represents the incremental changes in the pixel positions as the pixels are being generated. In a preferred embodiment, the binary data is translated into pixel position data which is then stored in a memory device. Any generated pixel data which cannot be stored in the machine cycle in which it is generated is re-routed for storage in later cycles.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式