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    • 2. 发明授权
    • CMOS frequency conversion using dual mixers for sideband suppression
    • CMOS频率转换使用双重混频器进行边带抑制
    • US06782247B2
    • 2004-08-24
    • US09825250
    • 2001-04-02
    • Christopher D. NilsonThomas G. McKay
    • Christopher D. NilsonThomas G. McKay
    • H04B126
    • H03D7/1441H03C3/40H03D7/1458H03D7/1466H03D7/1483H03D7/165H03D2200/0084
    • Disclosed is a frequency conversion circuit with sideband suppression in which a first mixer receives an in-phase signal (IFi) and is driven by a local oscillator having an in-phase (0°) oscillator signal (LOi), and produces two sideband signals (LO+IF, LO−IF). A second mixer receives a quadrature phase frequency signal (IFq+) and is driven by a local oscillator having a quadrature (180°) oscillator signal (LOq), and produces two sideband signals (LO+IFq, LO−IFq). One of the sidebands from the second mixer is 180° out of phase with respect to the same sideband from the first mixer. A signal combiner then receives and combines the two sidebands from the first mixer and the two sidebands from the second mixer, the signal combiner suppressing one sideband and enhancing the other sideband. In preferred embodiments, the mixers comprise MOSFET transistors and the signal combiner comprises capacitive elements.
    • 公开了一种具有边带抑制的频率转换电路,其中第一混频器接收同相信号(IFi)并且由具有同相(0°)振荡器信号(LOi)的本地振荡器驱动,并且产生两个边带信号 (LO + IF,LO-IF)。 第二混频器接收正交相位频率信号(IFq +)并且由具有正交(180°)振荡器信号(LOq)的本地振荡器驱动,并产生两个边带信号(LO + IFq,LO-IFq)。 来自第二混合器的边带中的一个相对于来自第一混合器的相同边带为180°异相。 然后,信号组合器接收并组合来自第一混频器的两个边带和来自第二混频器的两个边带,信号组合器抑制一个边带并增强另一个边带。 在优选实施例中,混频器包括MOSFET晶体管,信号组合器包括电容元件。
    • 4. 发明授权
    • Efficient AC coupled CMOS RF amplifier
    • US06570450B2
    • 2003-05-27
    • US09825252
    • 2001-04-02
    • Christopher D. NilsonThomas G. McKay
    • Christopher D. NilsonThomas G. McKay
    • H03F318
    • H03F1/308
    • Disclosed is a CMOS transistor amplifier for small RF signals which operates in a Class AB mode. The serially connected P channel and N channel transistors of the CMOS transistor pair have DC bias voltages applied to the control gates, and the small input signal is capacitively coupled to the gates of the CMOS transistor pair. In a preferred embodiment, the DC voltage bias for the P channel transistor is derived from a second P channel transistor which is approximately identical to the first P channel transistor in structure with the second P channel transistor serially connected with the current source and the voltage at the gate/drain of the transistor resistively coupled to the gate of the first P channel transistor. Similarly, the second bias circuit comprises a second N channel transistor which is approximately identical in structure to the first N channel transistor with the second N channel transistor serially connected with a current source and the bias voltage taken at the gate/drain of the second N channel transistor. The bias voltage is then applied through resistive means to the gate of the first N channel transistor.
    • 6. 发明授权
    • Seal ring structure for IC containing integrated digital/RF/analog circuits and functions
    • IC封装环结构,内含集成数字/射频/模拟电路及功能
    • US06492716B1
    • 2002-12-10
    • US09846335
    • 2001-04-30
    • Subhas BothraThomas G. McKayRavi Jhota
    • Subhas BothraThomas G. McKayRavi Jhota
    • H01L2302
    • H01L23/564H01L23/552H01L23/585H01L2924/0002H01L2924/3011H01L2924/00
    • Embodiments of the present invention provide a seal ring which includes a plurality of cuts separating the seal ring into seal ring portions which are disposed adjacent to different circuits in the integrated circuit die. The cuts reduce the noise coupling among the different circuits through the seal ring. To further isolate the sensitive RF/analog circuits from the noise generated by the digital circuit, the seal ring may be electrically (for dc noise) isolated from the substrate. This is accomplished, for instance, by inserting a polysilicon layer and gate oxide between the seal ring and the substrate. In addition, an n-well/p-well capacitor may be formed in series with the gate oxide, for instance, by implanting an n-well below the polysilicon layer in a p-type substrate. In this way, the seal ring provides substantially reduced noise coupling among the circuits but still maintains an effective wall around the periphery of the die to protect the circuits against moisture and ionic contamination penetration.
    • 本发明的实施例提供了一种密封环,其包括将密封环分隔成密封环部分的多个切口,所述密封环部分邻近集成电路管芯中的不同电路设置。 切割可以通过密封环减少不同电路之间的噪声耦合。 为了进一步将敏感的RF /模拟电路与数字电路产生的噪声隔离开,密封环可能是与基板隔离的电气(用于直流噪声)。 这通过例如在密封环和衬底之间插入多晶硅层和栅极氧化物来实现。 此外,n阱/ p阱电容器可以与栅极氧化物串联形成,例如通过在p型衬底中注入多晶硅层下面的n阱。 以这种方式,密封环在电路之间提供显着降低的噪声耦合,但仍然保持围绕芯片周边的有效壁,以保护电路免受潮湿和离子污染的渗透。